Freescale Semiconductor MCF52277 Reference Manual

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MCF52277 Reference Manual

Devices Supported:

MCF52274

MCF52277

Document Number: MCF52277RM

Rev. 1

04/2008

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Page 1 MCF52277 Reference Manual Devices Supported: MCF52274 MCF52277 Document Number: MCF52277RM Rev. 1 04/2008...
Page 2 Freescale Semiconductor product could Asia/Pacific: create a situation where personal injury or death may occur. Should Buyer Freescale Semiconductor Hong Kong Ltd.
Page 3 1.3.27 System Debug Support ......... . 1-10 MCF52277 Reference Manual, Rev. 1...
Page 4 Access Control Registers (ACRn) ........3-7 MCF52277 Reference Manual, Rev. 1...
Page 5 Cache Miss Fetch Algorithm/Line Fills....... . 5-9 Chapter 6 Static RAM (SRAM) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 6 Peripheral Behavior in Low-Power Modes......8-9 Chapter 9 Chip Configuration Module (CCM) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 7 11.1.2 Features............11-1 MCF52277 Reference Manual, Rev. 1...
Page 8 13.5.1 Arbitration ........... . 13-6 MCF52277 Reference Manual, Rev. 1...
Page 9 15.4 Initialization/Application Information ........15-18 MCF52277 Reference Manual, Rev. 1...
Page 10 17.7 Functional Description ..........17-24 MCF52277 Reference Manual, Rev. 1...
Page 11 19.1.3 Terminology ........... 19-3 MCF52277 Reference Manual, Rev. 1...
Page 12 20.5.5 Deviations from the EHCI Specifications ......20-73 MCF52277 Reference Manual, Rev. 1...
Page 13 21.4.10 8 bpp Mode Color STN Panel ........21-40 MCF52277 Reference Manual, Rev. 1...
Page 14 23.3.5 FlexCAN Error Counter Register (ERRCNT)......23-13 23.3.6 FlexCAN Error and Status Register (ERRSTAT)..... . 23-14 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 15 25.2 External Signal Description ..........25-5 MCF52277 Reference Manual, Rev. 1...
Page 16 26.3 Memory Map/Register Definition ......... 26-3 26.3.1 RTC Hours and Minutes Counter Register (RTC_HOURMIN) ... . 26-3 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 17 28.2.1 DMA Timer Mode Registers (DTMRn)....... 28-3 28.2.2 DMA Timer Extended Mode Registers (DTXMRn) ..... 28-4 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 18 29.4.6 Interrupts/DMA Requests ........29-33 MCF52277 Reference Manual, Rev. 1...
Page 19 31.1.3 Features............31-2 MCF52277 Reference Manual, Rev. 1...
Page 20 32.5.2 BDM Serial Interface ......... . . 32-20 MCF52277 Reference Manual, Rev. 1...
Page 21 33.5.2 Nonscan Chain Operation ........33-10 MCF52277 Reference Manual, Rev. 1...
Page 22: Mcf52277 Reference Manual,
MCF52277 Reference Manual, Rev. 1 xxii Freescale Semiconductor...
Page 23: About This Book
About This Book The primary objective of this reference manual is to define the MCF52277 processor for software and hardware developers. In addition, this manual supports the MCF52274. This book is written from the perspective of the MCF52277, and unless otherwise noted, the information applies also to the MCF52274.
Page 24 SDRAM controller. It begins with a general description and includes a description of signals involved in DRAM operations. The remainder of the chapter describes the programming model and signal timing, as well as the command set required for synchronous operations. MCF52277 Reference Manual, Rev. 0 xxiv Freescale Semiconductor...
Page 25 1149.1 standard and provides additional information specific to the device. For internal details and sample applications, see the IEEE 1149.1 document. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about ColdFire architecture. MCF52277 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 26: General Information
(Chapter 1) of a device’s reference manual. • Application notes—These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors. Additional literature is published as new processors become available. For a current list of ColdFire documentation, refer to http://www.freescale.com/coldfire.
Page 27 The only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length. MCF52277 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 28: Acronyms And Abbreviations
JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, first-out Least recently used Least-significant byte Least-significant bit Multiply accumulate unit, also Media access controller Most-significant byte Most-significant bit MCF52277 Reference Manual, Rev. 0 xxviii Freescale Semiconductor...
Page 29 Any control register (example VBR is the vector base register) MAC registers (ACC, MAC, MASK) Any address or data register Destination register w (used for MAC instructions only) Ry,Rx Any source and destination registers, respectively MCF52277 Reference Manual, Rev. 0 Freescale Semiconductor xxix...
Page 30 Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) Operations Arithmetic addition or postincrement indicator – Arithmetic subtraction or predecrement indicator Arithmetic multiplication MCF52277 Reference Manual, Rev. 0 Freescale Semiconductor...
Page 31: Revision History
Most significant word Revision History Table iii provides a revision history for this document. Table iii. MCF52277RM Revision History Revision Revision Description of Changes Number Date 04/2008 First public revision of this document. MCF52277 Reference Manual, Rev. 0 Freescale Semiconductor xxxi...
Page 32 MCF52277 Reference Manual, Rev. 0 xxxii Freescale Semiconductor...
Page 33: Mcf5227X Family Comparison
This document provides details of the MCF5227x microprocessor family, focusing on its highly diverse feature set. It was written from the perspective of the MCF52277 device. However, it also pertains to the MCF52274. See the following section for a summary of differences between the various devices of the MCF5227x family.
Page 34 Periodic Interrupt Timers (PIT) PWM Module • • Edge Port Module (EPORT) • • General Purpose I/O Module (GPIO) • • ® JTAG - IEEE 1149.1 Test Access Port • • Package 176 LQFP 196 MAPBGA MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 35: Block Diagram
Overview Block Diagram Figure 1-1 shows a top-level block diagram of the MCF52277 superset device. MCF52277 Version 2 ColdFire Core JTAG Oscillator Configurable Cache Serial Boot Facility Hardware EMAC Divide 128 K USB OTG eDMA Controller SRAM Instruction Bus Data Bus...
Page 36: Features
Overview Features The following is a brief summary of the functional blocks in the MCF52277 superset device followed by a module-by-module feature list. ® • Version 2 ColdFire Core with EMAC • Up to 159 Dhrystone 2.1 MIPS @ 166.67 MHz •...
Page 37: Phase Locked Loop (Pll)
• Core watchdog timer with a 2 (where n = 8–31) clock cycle selectable timeout period • Core fault reporting 1.3.8 Crossbar Switch Module • Concurrent access from different masters to different slaves MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 38: Liquid Crystal Display Controller (Lcdc)
Universal Serial Bus (USB) 2.0 On-The-Go (OTG) Controller • Support for full speed (FS) and low speed (LS) via an on-chip FS/LS transceiver • Uses 60 MHz reference clock based off of the system clock or from an external pin MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 39: Sdr/Ddr Sdram Controller
FlexCAN Module • Full implementation of the CAN protocol specification version 2.0B — Standard data and remote frames (up to 109 bits long) — Extended data and remote frames (up to 127 bits long) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 40: Real Time Clock
Input capture and reference compare modes 1.3.19 DMA Serial Peripheral Interface (DSPI) • Full-duplex, three-wire synchronous transfer • Up to three chip selects available • Master and slave modes with programmable master bit-rates MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 41: Pulse Width Modulation (Pwm) Module
Combinational path to provide wake-up from low power modes 1.3.24 Edge Port Module • Each pin can be individually configured as low level sensistive interrupt pin or edge-detecting interrupt pin (rising, falling, or both) • Exit stop mode via level-detect function MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 42: Dma Controller
General Purpose I/O interface • Up to 47 bits of GPIO for the MCF52274 (176 LQFP) • Up to 55 bits of GPIO for the MCF52277 (196 MAPBGA) • Bit manipulation supported via set/clear functions • Various unused peripheral pins may be used as GPIO 1.3.27...
Page 43: Internal Peripheral Space
0xFC04_4000 eDMA Controller 0xFC04_8000 Interrupt Controller 0 0xFC04_C000 Interrupt Controller 1 0xFC05_4000 Interrupt Controller IACK 0xFC05_8000 0xFC05_C000 DSPI 0xFC06_0000 UART0 0xFC06_4000 UART1 0xFC06_8000 UART2 0xFC07_0000 DMA Timer 0 0xFC07_4000 DMA Timer 1 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 1-11...
Page 44: Documentation
0xFC0B_8000 SDRAM Controller 0xFC0B_C000 0xFC0C_0000 Documentation Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire. MCF52277 Reference Manual, Rev. 1 1-12 Freescale Semiconductor...
Page 45: Introduction
Most pins that are muxed with GPIO will default to their GPIO functionality. See Table 2-1 for a list of the exceptions. Table 2-1. Special-Case Default Signal Functionality Default Signal FB_BE/BWE[3:0] FB_BE/BWE[3:0] FB_CS[3:0] FB_CS[3:0] FB_OE FB_OE FB_TA FB_TA MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 46 — — — SDVDD FB_BE/BWE[3:0] PBE[3:0] SD_DQM[3:0] — — SDVDD 29, 57, 27, 59 J3, N5, J1, L6 FB_CS[3:2] PCS[3:2] — — — SDVDD — B11, A11 FB_CS1 PCS1 SD_CS1 — — SDVDD MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 47 — — EVDD 5–2 D3, C3, D4, B1 LCD_D7 PLCDDL7 PWM7 — — EVDD — LCD_D6 PLCDDL6 PWM5 — — EVDD — LCD_D[5:2] PLCDDL[5:2] LCD_D[3:0] — — EVDD 175–172 A2, A3, B3, A4 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 48 CANRX U2RXD EVDD DSPI DSPI_PCS0/SS PDSPI3 U2RTS — EVDD DSPI_SIN PDSPI2 U2RXD SBF_DI EVDD DSPI_SOUT PDSPI1 U2TXD SBF_D0 — EVDD DSPI_SCK PDSPI0 U2CTS SBF_CK — EVDD UARTs U1CTS PUART7 SSI_BCLK LCD_CLS — EVDD MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 49 E6, E7, F5, F6, 111, 148, 176 G5, H9, J9, K8, K9 SD_VDD — — — — — — 14, 43, 44, 70, E8, E9, F9, G9, 113, 132, 146 H5, J5, J6, K6, K7 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 50: Signal Primary Functions
512 internal system bus clock cycles in response to any internal or external reset. (The exact time depends on how long it takes for the PLL to lock and/or the serial boot sequence to complete.) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 51: Pll And Clock Signals
These three-state outputs are the 24 lsbs of the internal 32-bit address bus. Data Bus FB_D[31:0] These three-state bidirectional signals provide the general purpose data path between the processor and all other devices. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 52: Sdram Controller Signals
The SD_DQMn should be connected to individual SDRAM DQM signals. Most SDRAMs associate DQM3 with the MSB, in which case SD_DQM3 should be connected to the SDRAM's DQM3 input. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 53: Serial Boot Facility Signals
Table 2-10. DMA Signals Signal Name Abbreviation Function DMA Request DREQ0 Asserted by an external device to request a DMA transfer. DMA Acknowledge DACK0 Asserted by processor to indicate DMA request has been recognized. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 54: Lcd Controller Signals
Waveform output for channel 7 of the PWM module. Also functions as an input for the emergency shutdown feature of the PWM. PWM[5,3,1,0] Outputs PWM[5,3,1,0] Waveform output for channels 5, 3, 1, and 0 respectively. MCF52277 Reference Manual, Rev. 1 2-10 Freescale Semiconductor...
Page 55: Universal Serial Bus (Usb) On-The-Go Signals
Signal Name Abbreviation Function Synchronous Serial DSPI_SOUT Provides the serial data from the DSPI, which may be driven on the Output rising or falling edge of DSPI_SCK. Each byte is sent msb first. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 2-11...
Page 56: Uart Module Signals
This clock signal is output from the device when it is the master. When in I S master mode, this signal is referred to as the oversampling clock. The frequency of SSI_MCLK is a multiple of the frame clock. MCF52277 Reference Manual, Rev. 1 2-12 Freescale Semiconductor...
Page 57: Dma Timer Signals
TDO changes on the falling edge of TCLK. BDM Signals Development Serial DSCLK Clocks the serial communication port to the BDM module during Clock packet transfers. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 2-13...
Page 58 DDATA[3:0] Display captured processor data and breakpoint status. The PSTCLK signal can be used by the development system to know when to sample DDATA[3:0]. Only present on the BGA device (MCF52277). Processor Status PST[3:0] Indicate core status, as shown in Table 2-22.
Page 59: Test Signals
These pins supply positive power to the RTC module. — ADC supply VDD_ADC Dedicated power supply for the touchscreen controller/ADC. — VSS_ADC Ground These pins are the negative supply (ground) for the device. — MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 2-15...
Page 60 Signal Descriptions MCF52277 Reference Manual, Rev. 1 2-16 Freescale Semiconductor...
Page 61: Introduction
Figure 3-1. V2 ColdFire Core Pipelines The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 62: Memory Map/Register Description
— Four 48-bit accumulator registers partitioned as follows: – Four 32-bit accumulators (ACC0–ACC3) – Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two 32-bit values for load and store operations (ACCEXT01 and ACCEXT23). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 63 MAC Accumulators 0–3 (ACC0–3) Undefined 4.2.3/4-6 0x80A, 0x80B 0x807 MAC Accumulator 0,1 Extension Bytes Undefined 4.2.4/4-7 (ACCext01) 0x808 MAC Accumulator 2,3 Extension Bytes Undefined 4.2.4/4-7 (ACCext23) 0x80E Condition Code Register (CCR) Undefined 3.2.4/3-6 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 64: Data Registers (D0–D7)
Figure 3-2. Data Registers (D0–D7) 3.2.2 Address Registers (A0–A6) These registers can be used as software stack pointers, index registers, or base address registers. They can also be used for word and longword operations. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 65: Supervisor/User Stack Pointers (A7 And Other_A7)
These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other instruction references to the stack pointer, explicit or implicit, access the active A7 register. NOTE The SSP is loaded during reset exception processing with the contents of location 0x0000_0000. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 66: Condition Code Register (Ccr)
Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand size; otherwise cleared. Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a subtraction; otherwise cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 67: Program Counter (Pc)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3-7. Vector Base Register (VBR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 68: Status Register (Sr)
The base address register includes a base address, write-protect bit, address space mask bits, and an enable bit. RAMBAR determines the base address of the on-chip RAM. For more information, refer to Section 6.2.1, “SRAM Base Address Register (RAMBAR)”. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 69: Functional Description
In these diagrams, the internal structure of the instruction fetch and operand execution pipelines is shown: Opword Core Bus Address Extension 1 FIFO Core Bus Read Data Extension 2 Figure 3-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 70 Ry,<mem>x For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and fetching of the required register operands (OC) from the dual-ported register file, while the actual MCF52277 Reference Manual, Rev. 1 3-10 Freescale Semiconductor...
Page 71 ) is optimized to support a two-cycle execution time. The following example move.l <mem>y,Rx Figure 3-12 shows an effective address of the form <ea>y = (d16,Ay), i.e., a 16-bit signed displacement added to a base register Ay. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-11...
Page 72 For register-to-memory (store) operations, the stage functions (DS/OC, AG/EX) are effectively performed simultaneously allowing single-cycle execution. See Figure 3-14 where the effective address is of the form <ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax. MCF52277 Reference Manual, Rev. 1 3-12 Freescale Semiconductor...
Page 73 Figure 3-15 depict the execution templates for these three classes of instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown progressing down the operand execution pipeline. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-13...
Page 74: Instruction Set Architecture (Isa_A+)
ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three areas: 1. Enhanced support for byte and word-sized operands 2. Enhanced support for position-independent code 3. Miscellaneous instruction additions to address new functionality MCF52277 Reference Manual, Rev. 1 3-14 Freescale Semiconductor...
Page 75: Exception Processing Overview
(IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to special locations within the interrupt controller’s address space with the interrupt level encoded in the address. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-15...
Page 76 Fault Unimplemented line-A opcode 0x02C Fault Unimplemented line-F opcode 0x030 Next Debug interrupt 0x034 — Reserved 0x038 Fault Format error 15–23 0x03C–0x05C — Reserved 0x060 Next Spurious interrupt 25–31 0x064–0x07C — Reserved MCF52277 Reference Manual, Rev. 1 3-16 Freescale Semiconductor...
Page 77: Exception Stack Frame Definition
There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other exceptions. See Table 3-7. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-17...
Page 78: Processor Exceptions
Accordingly, the PC contained in the exception stack frame merely represents the location in the program when the access error was signaled. All programming model updates associated with the write instruction are completed. The NOP instruction can collect access errors for writes. This instruction delays its MCF52277 Reference Manual, Rev. 1 3-18 Freescale Semiconductor...
Page 79: Address Error Exception
PC-relative change-of-flow instructions Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR) Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ) Logical OR (OR) Subtract (SUB), Subtract Extended (SUBX) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-19...
Page 80 1. The instruction before the stop executes and then generates a trace exception. In the exception stack frame, the PC points to the stop opcode. 2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate operand from the instruction. MCF52277 Reference Manual, Rev. 1 3-20 Freescale Semiconductor...
Page 81: Debug Interrupt
(3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-21...
Page 82: Interrupt Exception
0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault state. MCF52277 Reference Manual, Rev. 1 3-22 Freescale Semiconductor...
Page 83 FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core. 0 FPU execute engine not present in core. (This is the value used for this device.) 1 FPU execute engine is present in core. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-23...
Page 84 Information loaded into D1 defines the local memory hardware configuration as shown in the figure below. BDM: Load: 0x081 (D1) Access: User read-only BDM read-only Store: 0x181 (D1) CLSZ CCAS CCSZ Reset MBSZ SRAMSZ Reset Figure 3-19. D1 Hardware Configuration Info MCF52277 Reference Manual, Rev. 1 3-24 Freescale Semiconductor...
Page 85: Instruction Execution Timing
• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing a read-modify-write function is denoted as (1/1). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-25...
Page 86: Move Instruction Execution Times
Table 3-13 lists timings for MOVE.L. NOTE For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode. MCF52277 Reference Manual, Rev. 1 3-26 Freescale Semiconductor...
Page 87 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — (d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — — (d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — #xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — — MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-27...
Page 88 — — AND.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) AND.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — ANDI.L #imm,Dx 1(0/0) — — — — — — — MCF52277 Reference Manual, Rev. 1 3-28 Freescale Semiconductor...
Page 89 3(1/1) — SUBI.L #imm,Dx 1(0/0) — — — — — — — SUBQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — SUBX.L Dy,Dx 1(0/0) — — — — — — — MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-29...
Page 90: Miscellaneous Instruction Execution Times
The execution time for STOP is the time required until the processor begins sampling continuously for interrupts. PEA execution times are the same for (d16,PC). PEA execution times are the same for (d8,PC,Xn*SF). MCF52277 Reference Manual, Rev. 1 3-30 Freescale Semiconductor...
Page 91: Emac Instruction Execution Times
(1/0) (1/0) 4(0/0) Effective address of (d16,PC) not supported Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] equals 1---, -11-, --11) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 3-31...
Page 92 — — — — — 5(1/0) — — — — — Table 3-19. Bcc Instruction Execution Times Forward Forward Backward Backward Opcode Taken Not Taken Taken Not Taken 3(0/0) 1(0/0) 2(0/0) 3(0/0) MCF52277 Reference Manual, Rev. 1 3-32 Freescale Semiconductor...
Page 93: Introduction
The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module (Figure 4-1). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 94 ( )x i k b 0 ( )x i ( ) b 1 ( )x i 1 b 2 ( )x i 2 b 3 ( )x i 3 – – – – Eqn. 4-2 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 95: Memory Map/Register Definition
MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator is used to form the general overflow flag, MACSR[V]. After set, each flag remains set until V is cleared by a move.l, MACSR instruction or the accumulator is loaded directly. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 96 MULS and MULU instructions. Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 97: Mask Register (Mask)
This minimizes the addressing support required for filtering, convolution, or any routine that implements a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be included in all memory effective address calculations. The syntax is as follows: mac.sz Ry,RxSF,<ea>y&,Rw MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 98: Accumulator Registers (Acc0–3)
Performs a simple AND with the operand address for MAC instructions. MASK 4.2.3 Accumulator Registers (ACC0–3) The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers form the entire 48-bit result. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 99: Accumulator Extension Registers (Accext01, Accext23)
Table 4-6. ACCext01 Field Descriptions Field Description 31–24 Accumulator 0 upper extension byte ACC0U 23–16 Accumulator 0 lower extension byte ACC0L 15–8 Accumulator 1 upper extension byte ACC1U 7–0 Accumulator 1 lower extension byte ACC1L MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 100: Functional Description
For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 101 Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]} if MACSR[6:5] == 10 /* unsigned integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} The four accumulators are represented as an array, ACCn, where n selects the register. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 102: Fractional Operation Mode
16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L. • If R0.L is less than 0x8000, the result is truncated to the value of R0.U. • If R0.L is greater than 0x8000, the upper word is incremented (rounded up). MCF52277 Reference Manual, Rev. 1 4-10 Freescale Semiconductor...
Page 103 ; save the accumulator extensions move.l accext23,d5 move.l mask,d6 ; save the address mask movem.l #0x00ff,(a7) ; move the state to memory This code performs the EMAC state restore: EMAC_state_restore: MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 4-11...
Page 104: Emac Instruction Set Summary
MASK,Rx Store MAC Mask Reg Writes the contents of the MASK to a CPU register move.l {Ry,#imm},ACCext01 Loads the accumulator 0,1 extension bytes with a 32-bit Load Accumulator Extensions 01 operand MCF52277 Reference Manual, Rev. 1 4-12 Freescale Semiconductor...
Page 105: Emac Instruction Execution Times
1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is performed, the recently updated accumulator 0 value is available. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 4-13...
Page 106: Data Representation
For the EMAC, assemblers support this syntax and no explicit reference to an accumulator is interpreted as a reference to ACC0. Assemblers also support syntaxes where the destination accumulator is explicitly defined. MCF52277 Reference Manual, Rev. 1 4-14 Freescale Semiconductor...
Page 107 = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ if (product[63] == 1) then result[47:0] = 0xffff_8000_0000 else result[47:0] = 0x0000_7fff_ffff MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 4-15...
Page 108 (MACSR.OMC == 0 || MACSR.PAVn == 0) then { MACSR.PAVn = 0 if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], 0x0000} if (U/Lx == 1) MCF52277 Reference Manual, Rev. 1 4-16 Freescale Semiconductor...
Page 109 MACSR.PAVn = 0 /* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {0x0000, Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} if (U/Lx == 1) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 4-17...
Page 110 (accumulationOverflow == 1) then {MACSR.PAVn = 1 MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ MCF52277 Reference Manual, Rev. 1 4-18 Freescale Semiconductor...
Page 111 ACCx[47:0] = result[47:0] MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1 break; MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 4-19...
Page 112 Enhanced Multiply-Accumulate Unit (EMAC) MCF52277 Reference Manual, Rev. 1 4-20 Freescale Semiconductor...
Page 113: Introduction
[31:12] for a split configuration of the fetch address from the local bus to determine if a cache hit has occurred. If the desired address is mapped into the cache memory, the MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 114: Memory Map/Register Definition
Memory Map/Register Definition Three supervisor registers define the operation of the cache and local bus controller: the cache control register (CACR) and two access control registers (ACR0, ACR1). Table 5-1 below shows the memory map MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 115: Cache Control Register (Cacr)
Cache enable. The memory array of the cache is enabled only if CENB is asserted. This bit, along with the DISI CENB (disable instruction caching) and DISD (disable data caching) bits, control the cache configuration. 0 Cache disabled 1 Cache enabled Table 5-3 describes cache configuration. 30–29 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 116 CLNF[1:0] for non-cacheable accesses. Non-cacheable accesses are never written into the memory array. See Table 5-7. 0 Disable burst fetches on non-cacheable accesses 1 Enable burst fetches on non-cacheable accesses MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 117 Data Cache 8 KByte direct-mapped write-through data cache (uses all of tag and storage arrays) Table 5-4 shows the relationship between CACR[DISI, DISD, INVI, & INVD] and setting the cache invalidate all bit (CACR[CINV]). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 118: Access Control Registers (Acr0, Acr1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CM BWE Reset – – – – – – – – – – – – – – – – – – – – – Figure 5-3. Access Control Registers (ACRn) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 119: Functional Description
The cache processes any fetch access in the normal manner. 5.3.1 Interaction with Other Modules Because the cache and high-speed SRAM module are connected to the ColdFire core's local data bus, certain user-defined configurations can result in simultaneous fetch processing. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 120: Memory Reference Attributes
A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting CACR[CINV] before the cache can be enabled. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 121: Cache Miss Fetch Algorithm/Line Fills
Generally, longword references are used for sequential instruction fetches. If the processor branches to an odd word address, a word-sized instruction fetch is generated. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 122 All instruction fetches are word or longword in size, and not loaded into the line-fill buffer Non-cacheable Instruction fetch size is defined by Table 5-6 loaded into the line-fill buffer, but are never written into the memory array. MCF52277 Reference Manual, Rev. 1 5-10 Freescale Semiconductor...
Page 123: Introduction
• One 128 Kbyte SRAM • Single-cycle access • Physically located on the processor's high-speed local bus • Memory location programmable on any 0-modulo-128 Kbyte address • Byte, word, and longword address capabilities MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 124: Memory Map/Register Description
SRAM memory. For example, writes to addresses 0x8000_0000 and 0x8002_0000 modify the same memory location. System software should ensure SRAM address pointers do not exceed the SRAM size to prevent unwanted overwriting of SRAM. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 125 0 Allows read and write accesses to the SRAM module from non-core masters. 1 Allows only read accesses to the SRAM module from non-core masters. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 126: Initialization/Application Information
The following code segment describes how to initialize the SRAM. The code sets the base address of the SRAM at 0x8000_0000 and initializes the SRAM to zeros. RAMBASE EQU 0x80000000 ;set this variable to 0x80000000 RAMVALID EQU 0x00000001 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 127: Power Management
Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power dissipation. Table 6-3 shows examples of typical RAMBAR settings. Table 6-3. Typical RAMBAR Setting Examples Data Contained in SRAM RAMBAR[7:0] Instruction Only 0x2B Data Only 0x35 Instructions and Data 0x21 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 128 Static RAM (SRAM) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 129: Introduction
(SBF controls many configuration options, clocks to the SDRAMC controller are disabled when the device is in limp mode, and the clocks to individual modules may be disabled via the peripheral power management registers as described in Chapter 8, “Power Management”). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 130 When loading boot code via the SBF, the device is clocked by the main oscillator (f The LCD controller is also given a 32 Hz clock for the cursor blink counter. Figure 7-1. Device Clock Connections MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 131: Block Diagram
• Direct clocking of system by input clock, bypassing the PLL • Loss-of-lock reset • Reference crystal oscillator for the real time clock (RTC) module. Input clock used is programmable within the RTC. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 132: Modes Of Operation
However, it is able to capture a wake-up event to release the processor from limp mode. When switching from limp mode to normal functional mode, you must ensure that any peripheral transactions in progress are allowed to complete to avoid data loss or corruption. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 133: Memory Map/Register Definition
There is also a fast wake-up option for quickly enabling the system clocks during stop recovery (LPCR[FWKUP]). This eliminates the wake-up recovery time but at the risk of sending a potentially unstable clock to the system. Memory Map/Register Definition The PLL programming model consists of the following: MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 134: Pll Control Register (Pcr)
× PFDR Eqn. 7-1 where f is the PLL input frequency from the internal oscillator or EXTAL clock source (defined by the selected chip configuration). 23–20 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 135 Maximum Peripheral Clock) 8 × OUTDIV1 + 7 — 0001 (CPU freq ÷ 8) 4 × OUTDIV1 + 3 — 0011 (CPU freq ÷ 4) ≠ 0 0111 (Disabled) (Enabled) 1111 (Disabled) (Disabled) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 136: Pll Status Register (Psr)
PFDR must also be selected such that the VCO frequency (f 300–540 MHz. The other clocks on the processor are configurable in a similar fashion. However, there are various dependencies. See Section 7.2.1, “PLL Control Register (PCR),” for details. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 137: Lock Conditions
PLL has re-locked, the PLL does not update the PSR[LOCKS] status bit. The LOCKS status bit is sticky, and the user must clear it before the PLL can write the register again. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 138: System Clock Modes
USB_CLKIN in the USB OTG column indicates that the USB On-the-Go module receives its clock from the USB_CLKIN signal rather than the PLL output. Table 7-5. MCF52277 Clocking Scenarios (MHz) Input Reference/ OUTDIV1...
Page 139: Clock Operation During Reset
Clock Module Table 7-5. MCF52277 Clocking Scenarios (MHz) (continued) Input Reference/ OUTDIV1 ColdFire Internal Bus PCR[PFDR] OUTDIV5 USB OTG (Core ÷ 2) Crystal Frequency Core Parallel Boot into Limp Mode (BOOTMOD = 10 and FB_A19 = 1) 166.67 83.33 —...
Page 140 Clock Module MCF52277 Reference Manual, Rev. 1 7-12 Freescale Semiconductor...
Page 141: Introduction
0xFC0A_0012 Clock Divider Register (CDR) 0x0001 10.3.6/10-13 User access to supervisor only address locations have no effect and result in a bus error The MISCCR and CDR registers are described in Chapter 9, “Chip Configuration Module (CCM).” MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 142: Wake-Up Control Register (Wcr)
Table 8-2. WCR Field Descriptions Field Description Enable low-power mode entry. The mode entered is specified in WCR[LPMD]. ENBWCR 0 Low-power mode entry is disabled 1 Low-power mode entry is enabled. Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 143: Peripheral Power Management Set Register (Ppmsr)
PPMR to set, disabling all peripheral module clocks. Reads of these registers return all zeroes. Address: 0xFC04_002C (PPMSR) Access: Supervisor Write-only SAMCD SMCD Reset: Figure 8-2. Peripheral Power Management Set Register (PPMSR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 144: Peripheral Power Management Clear Register (Ppmcr)
Because the operation of the crossbar switch and the system control module (SCM) are fundamental to the operation of the device, the clocks for these modules cannot be disabled. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 145 SDRAM Controller CD47 CD48 Address: 0xFC04_0034 (PPMLR) Access: Supervisor read/write CD31 CD30 CD29 CD28 CD26 CD25 CD24 CD23 CD22 CD21 CD19 CD18 CD17 Reset CD15 Reset Figure 8-5. Peripheral Power Management Low Registers (PPMLR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 146 Take extreme caution when setting PPMR[CD40] to disable clocking of the CCM, reset controller, and power management modules. This may disable logic to reset the chip and disable the external bus monitor or other logic contained within these blocks. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 147: Low-Power Control Register (Lpcr)
See Section 8.2.4, “Peripheral Power Management Registers (PPMHR & PPMLR),” for more information. A peripheral may be disabled at any time and remains disabled during any low-power mode of operation. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 148: Limp Mode
Wait mode is intended to stop only the CPU and memory clocks until a wake-up event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, causing the CPU to exit from wait mode. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 149: Peripheral Behavior In Low-Power Modes
Chip Configuration Module Enabled Enabled Stopped Reset Controller Enabled Reset Enabled Reset Stopped Reset System Control Module Enabled Reset Enabled Reset Enabled GPIO Module Enabled Enabled Stopped Interrupt controller Enabled Interrupt Enabled Interrupt Stopped Interrupt MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 150 The ColdFire core disables during any low-power mode. No recovery time is required when exiting any low-power mode. 8.3.4.2 Internal SRAM The SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. MCF52277 Reference Manual, Rev. 1 8-10 Freescale Semiconductor...
Page 151: Clock Module
Depending on the setting of the CWCR[CWRI] field, a core watchdog timeout may reset the device. Other settings of the CWRI field may enable a core watchdog interrupt and upon a watchdog timeout, this MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 152 EDMA_EEIR[EEIn] is set, and an interrupt generates when any of the EDMA_ESR bits become set. The eDMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode. MCF52277 Reference Manual, Rev. 1 8-12 Freescale Semiconductor...
Page 153 In stop mode, there is a pen-down event that can generate an interrupt to wake-up the device. Upon exiting stop mode, the touschreen controller resumes operation from the state prior to stop mode entry. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 154: Lcd Controller
CAN bus (11 consecutive recessive bits), and only then does it search for the correct conditions to stop. • Trying to stop the FlexCAN immediately after reset is allowed only after basic initialization has been performed. MCF52277 Reference Manual, Rev. 1 8-14 Freescale Semiconductor...
Page 155 8.3.4.23 UART Modules (UART0–2) In wait and doze modes, the UARTs are unaffected and may generate an interrupt to exit these low-power modes. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 8-15...
Page 156 The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and not affected by the system clock. The JTAG cannot generate an event to cause the processor to exit any low-power mode. Toggling TCLK during any low-power mode increases the system current consumption. MCF52277 Reference Manual, Rev. 1 8-16 Freescale Semiconductor...
Page 157: Introduction
The available bus control signals include FB_R/W, FB_TS, FB_TA, FB_OE, and FB_BE/BWE[3:0]. Up to six chip selects can be programmed to select and control external devices and to provide bus cycle termination. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 158: External Signal Descriptions
Register Access Reset Value Section/Page (bits) Supervisor Access Only Registers 0xFC0A_0004 Chip Configuration Register (CCR) See Section 9.3.1/9-3 0xFC0A_0008 Reset Configuration Register (RCON) 0x000D 9.3.2/9-4 0xFC0A_000A Chip Identification Register (CIR) See Section 9.3.3/9-5 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 159: Chip Configuration Register (Ccr)
Note: See DRAMSEL bit description for reset value. Note: CCR[7:0] reset value depends upon chosen reset configuration. Default reset value (BOOTMOD = 00 or 01) is the value of RCON[7:0]. Figure 9-2. Chip Configuration Register (CCR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 160: Reset Configuration Register (Rcon)
RCON values can be overridden only during reset configuration (see Section 9.4.1, “Reset Configuration”) if the external BOOTMOD[1:0] pins are driven to 10 or 11. RCON is a read-only register and contains the same fields as the CCR register, except for DRAMSEL. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 161: Chip Identification Register (Cir)
SSI/timer DMA mux control and other miscellaneous control functionality. Address: 0xFC0A_0010 (MISCCR) Access: Supervisor read/write LCDC LIMP Reset See Note See Note Note: Reset value depends on RCON type. See Table 9-6. Figure 9-5. Miscellaneous Control Register (MISCCR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 162 Bus monitor external enable bit. Enables the bus monitor to operate during external FlexBus cycles 0 Bus monitor disabled on external FlexBus cycles 1 Bus monitor enabled on external FlexBus cycles MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 163 USB clock source. Selects between the PLL and the external USB_CLKIN external pin as the clock source for USBSRC the serial and ULPI interfaces of the USB module. 0 USB_CLKIN pin drives USB serial interface clocks. 1 PLL drives USB serial interface clocks. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 164: Clock-Divider Register (Cdr)
USB OTG module. Address: 0xFC0A_0014 (UOCSR) Access: Supervisor read/write CRG_ DCR_ DPPD DMPD DPPU VBUS VBUS AVLD BVLD VVLD SEND WKUP UOMIE XPDE Reset Figure 9-7. USB On-the-Go Controller Status Register (UOCSR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 165: Functional Description
1 On-chip 50 kΩ pull-downs enabled on OTG D+ and D- transceiver pins of on-chip transceiver. Functional Description 9.4.1 Reset Configuration During reset, the pins for the reset override functions are immediately configured to known states. Table 9-10 shows the states of the external pins while in reset. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 166 8-bit (split bus) or 32-bit (unified bus) 16-bit split bus FB_A18 Output Pad Drive Strength All output pins RCON[4] Low Drive Strength High Drive Strength FB_A19 PLL Mode (none) RCON[5] PLL mode Limp mode MCF52277 Reference Manual, Rev. 1 9-10 Freescale Semiconductor...
Page 167 Affected CCM SBF_RCON Bits Pin(s) Affected Function Register Bit(s) Mnemonic Bit Num BOOTPS 31:30 Boot Port Size 32-bit port FB_D[31:0] CCR[3:2] 8-bit port 16-bit port 16-bit port DRAMSEL SDR/DDR Config (none) CCR[8] MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 9-11...
Page 168 OSCMODE Oscillator Mode (none) CCR[1] Crystal oscillator mode Oscillator bypass mode LIMP Limp Mode (none) CCR[5] PLL mode Limp mode External Bus Monitor Enable (none) CCR[11] Bus monitor disabled Bus monitor enabled MCF52277 Reference Manual, Rev. 1 9-12 Freescale Semiconductor...
Page 169 USB VBUS Overcurrent Sense Polarity USB_VBUS_OC MISCCR[1] USB_VBUS_OC is active-low USB_VBUS_OC is active-high USBSRC USB Clock Source USB_CLKIN MISCCR[0] USB_CLKIN pin drives USB serial interface clock PLL drives USB serial interface clocks MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 9-13...
Page 170: Boot Configuration
RCON pin is asserted. 9.4.4 Chip Select Configuration The chip select (FB_CS[5:4]) configuration is selected during reset and reflected in the CCR[CSC] field. After reset is exited, the chip select configuration cannot be changed. MCF52277 Reference Manual, Rev. 1 9-14 Freescale Semiconductor...
Page 171: Low Power Configuration
After reset, the device can be configured for operation during the low power modes using the low power control register (LPCR). For more information on this register, see Section 8.2.5, “Low-Power Control Register (LPCR).” MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 9-15...
Page 172 Chip Configuration Module (CCM) MCF52277 Reference Manual, Rev. 1 9-16 Freescale Semiconductor...
Page 173: Introduction
SPI memory clock frequency, configures an extended set of power-up options for the processor, and optionally loads code into the on-chip SRAM. Through interaction with the reset controller, the SBF performs these actions so that the chip is properly configured after exiting the reset state. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 10-1...
Page 174: Features
0xFC0A_0020 SBFCR—Serial Boot Facility Control Register See Section 10.3.2/10-3 10.3.1 Serial Boot Facility Status Register (SBFSR) The read-only SBFSR register reflects the amount of boot code loaded through the external SPI memory. MCF52277 Reference Manual, Rev. 1 10-2 Freescale Semiconductor...
Page 175: Serial Boot Facility Control Register (Sbfcr)
BLDIV field is written. Any subsequent writes to this field prior to a power-on reset event terminate without effect. 0 SBF uses the standard command READ 1 SBF uses the FAST_READ command MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 10-3...
Page 176: Functional Description
SPI memory output switches from high-impedance to logic 0. 4. The SBF shifts the standard SPI memory read command (0x03) followed by repeated 0x00 address ÷ 67. bytes to the SPI memory at f MCF52277 Reference Manual, Rev. 1 10-4 Freescale Semiconductor...
Page 177: Reset Configuration And Optional Boot Load
After boot load is complete or if no boot load is requested (SBFSR[BLL] = 0), the following steps complete the serial boot process: 1. The acquired configuration data is driven to the appropriate modules. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 10-5...
Page 178: Initialization Information
CODE_BYTE_[4 × (BLL + 1) - 1] This assumes SBFSR[BLL] is set. If BLL is cleared, the SBF does not access data at these addresses. Start of the user code copied into the on-chip SRAM. MCF52277 Reference Manual, Rev. 1 10-6 Freescale Semiconductor...
Page 179: Fast_Read Feature Initialization
FAST_READ feature altogether. Even when the delays within the processor itself are minimized, the actual SPI memories may have similarly untenable electrical specifications (data input setup and output valid times). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 10-7...
Page 180 Serial Boot Facility (SBF) MCF52277 Reference Manual, Rev. 1 10-8 Freescale Semiconductor...
Page 181: Introduction
— Core watchdog timer — Phase locked-loop (PLL) loss of lock — Software • Software-assertable RSTOUT pin independent of chip-reset state • Software-readable status flags indicating the cause of the last reset MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 11-1...
Page 182: External Signal Description
Table 11-2. Reset Controller Memory Map Width Address Register Access Reset Value Section/Page (bits) 0xFC0A_0000 Reset Control Register (RCR) 0x00 11.3.1/11-3 0xFC0A_0001 Reset Status Register (RSR) See Section 11.3.2/11-3 MCF52277 Reference Manual, Rev. 1 11-2 Freescale Semiconductor...
Page 183: Reset Control Register (Rcr)
RSR can be read at any time. Writing to RSR has no effect. Address: 0xFC0A_0001 (RSR) Access: User read-only SOFT CORE Reset: Reset Reset Reset Reset Reset Dependent Dependent Dependent Dependent Dependent Figure 11-3. Reset Status Register (RSR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 11-3...
Page 184: Functional Description
Internal byte, word, or longword writes are guaranteed to complete without data corruption when a synchronous reset occurs. External writes, including longword writes to 16-bit ports, are also guaranteed to complete. MCF52277 Reference Manual, Rev. 1 11-4 Freescale Semiconductor...
Page 185: Reset Control Flow
Figure 11-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 11-5...
Page 186 (Parallel RCON) Figure 11-4. Reset Control Flow 11.4.2.1 Synchronous Reset Requests In this discussion, the reference in parentheses refer to the state numbers in Figure 11-4. All cycle counts given are approximate. MCF52277 Reference Manual, Rev. 1 11-6 Freescale Semiconductor...
Page 187: Concurrent Resets
If other reset sources are asserted after the RSR status bits have been latched (4 or 5), the device is held in reset (9 or 10) until all sources have negated and the subsequent sources are not reflected in the RSR contents. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 11-7...
Page 188 Reset Controller Module MCF52277 Reference Manual, Rev. 1 11-8 Freescale Semiconductor...
Page 189: Introduction
— Core watchdog control register (CWCR) for watchdog timer control — Core watchdog service register (CWSR) to service watchdog timer — SCM interrupt status register (SCMISR) to service a bus fault or watchdog interrupt • Core fault reporting registers MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 12-1...
Page 190: Memory Map/Register Definition
The MPR specifies five 4-bit fields defining the access-privilege level associated with a bus master in the device to the various peripherals listed in Table 12-4. The register provides one field per bus master. MCF52277 Reference Manual, Rev. 1 12-2 Freescale Semiconductor...
Page 191: Peripheral Access Control Registers (Pacrx)
Each of the peripherals has a four-bit PACRn field that defines the access levels supported by the given module. Eight PACRs are grouped together to form a 32-bit PACRx register (PACRA-PACRI). At reset the SCM (PACR0) does not allow access from untrusted masters, while the other peripherals do. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 12-3...
Page 192 Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 Figure 12-7. Peripheral Access Control Register E (PACRE) MCF52277 Reference Manual, Rev. 1 12-4...
Page 193 Real-Time Clock PACR16 SCM (CWT & Core Fault Registers) PACR17 eDMA Controller PACR18 Interrupt Controller 0 PACR19 Interrupt Controller 1 PACR21 Interrupt Controller IACK PACR22 PACR23 DSPI PACR24 UART0 PACR25 UART1 PACR26 UART2 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 12-5...
Page 194 1 This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor access attribute, and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. MCF52277 Reference Manual, Rev. 1 12-6 Freescale Semiconductor...
Page 195: Core Watchdog Control Register (Cwcr)
0 Core watchdog timer stops counting if the core is halted. 1 Core watchdog timer continues to count even while the core is halted. Core watchdog timer enable. 0 CWT is disabled. 1 CWT is enabled. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 12-7...
Page 196: Core Watchdog Service Register (Cwsr)
SCMISR provides a program visible interrupt request from the watchdog timer. During the interrupt service routine that manages this interrupt, the source must be explicitly cleared by writing a 0x01 to the SCMISR. MCF52277 Reference Manual, Rev. 1 12-8 Freescale Semiconductor...
Page 197: Burst Configuration Register (Bcr)
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GBR GBW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-15. Burst Configuration Register (BCR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 12-9...
Page 198: Core Fault Address Register (Cfadr)
Indicates the faulting address of the last core access terminated with an error response. ADDR 12.2.8 Core Fault Interrupt Enable Register (CFIER) The CFIER register enables the system bus-error interrupt. See Chapter 15, “Interrupt Controller Modules,” for more information of the interrupt controller. MCF52277 Reference Manual, Rev. 1 12-10 Freescale Semiconductor...
Page 199: Core Fault Location Register (Cfloc)
1 Error occurred within the core. 6–0 Reserved, must be cleared. 12.2.10 Core Fault Attributes Register (CFATR) The read-only CFATR register captures the processor’s attributes of the last faulted core access to the system bus. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 12-11...
Page 200: Core Fault Data Register (Cfdtr)
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 12-20. Core Fault Data Register (CFDTR) MCF52277 Reference Manual, Rev. 1 12-12...
Page 201: Functional Description
To prevent the core watchdog timer from interrupting or resetting, the CWSR register must be serviced by performing the following sequence: 1. Write 0x55 to CWSR. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 12-13...
Page 202: Core Data Fault Recovery Registers
The details on the core fault recovery registers are provided in the above sections. These registers are used to capture fault recovery information on any processor-initiated system bus cycle terminated with an error. MCF52277 Reference Manual, Rev. 1 12-14 Freescale Semiconductor...
Page 203: Overview
MCF5227x family bus architecture showing the crossbar switch configuration. ColdFire eDMA Serial Boot Core Controller Controller On-the-Go Master Modules Crossbar Switch Slave Modules FlexBus/SDRAM SRAM On-chip Slave Controller Backdoor Peripherals Figure 13-1. Bus Architecture Block Diagram MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 13-1...
Page 204: Features
— Allows concurrent accesses from different masters to different slaves — Slave arbitration attributes configured on a slave by slave basis • 32 bits wide and supports byte, word (2 byte), longword (4 byte), and 16 byte burst transfers MCF52277 Reference Manual, Rev. 1 13-2 Freescale Semiconductor...
Page 205: Modes Of Operation
The priority registers (XBS_PRSn) set the priority of each master port on a per slave port basis and reside in each slave port. The priority register can be accessed only with 32-bit accesses. After the MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 206 Master 4 (LCD Controller) priority. See M7 description. 15–7 Reserved, must be cleared. 6–4 Master 1 (eDMA) priority. See M7 description. Reserved, must be cleared. 2–0 Master 0 (ColdFire core) priority. See M7 description. MCF52277 Reference Manual, Rev. 1 13-4 Freescale Semiconductor...
Page 207: Xbs Control Registers (Xbs_Crsn)
01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. 11 Reserved. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 13-5...
Page 208: Functional Description
• An IDLE cycle • A non-IDLE cycle to a location other than the current slave port. MCF52277 Reference Manual, Rev. 1 13-6 Freescale Semiconductor...
Page 209: Initialization/Application Information
No initialization is required by or for the crossbar switch. Hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state. Settings and priorities should be programmed to achieve maximum system performance. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 13-7...
Page 210 Crossbar Switch (XBS) MCF52277 Reference Manual, Rev. 1 13-8 Freescale Semiconductor...
Page 211: Introduction
NOTE The GPIO functionality of the port IRQ pins is selected by the edge port module. They are shown in the below figure only for completeness. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-1...
Page 212: Overview
• UART • 32-bit DMA timers 14.1.3 Features The ports module includes these distinctive features: • Control of primary function use — On all supported GPIO ports, except those for FB_AD[31:0] pins MCF52277 Reference Manual, Rev. 1 14-2 Freescale Semiconductor...
Page 213: External Signal Description
Most pins that are muxed with GPIO will default to their GPIO functionality. See Table 14-1 for a list of the exceptions. Table 14-1. Special-Case Default Signal Functionality Default Signal FB_BE/BWE[3:0] FB_BE/BWE[3:0] FB_CS[3:0] FB_CS[3:0] FB_OE FB_OE FB_TA FB_TA FB_R/W FB_R/W FB_TS FB_TS MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-3...
Page 214 — — SDVDD FB_CS0 PCS0 — — — SDVDD FB_OE PFBCTL3 — — — SDVDD FB_TA PFBCTL2 — — SDVDD FB_R/W PFBCTL1 — — — SDVDD FB_TS PFBCTL0 DACK0 — — SDVDD MCF52277 Reference Manual, Rev. 1 14-4 Freescale Semiconductor...
Page 215 A2, A3, B3, A4 LCD_D1 PLCDDL1 PWM3 — — EVDD — LCD_D0 PLCDDL0 PWM1 — — EVDD — LCD_ACD/ PLCDCTL3 LCD_SPL_SPR — — EVDD LCD_OE LCD_FLM/ PLCDCTL2 — — — EVDD LCD_VSYNC MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-5...
Page 216 — EVDD U1RTS PUART6 SSI_FS LCD_PS — EVDD U1RXD PUART5 SSI_RXD — — EVDD U1TXD PUART4 SSI_TXD — — EVDD U0CTS PUART3 DT1OUT USB_VBUS_EN — EVDD U0RTS PUART2 DT1IN USB_VBUS_OC — EVDD MCF52277 Reference Manual, Rev. 1 14-6 Freescale Semiconductor...
Page 217 — — — — VDD_PLL — — — — — — VDD_USB — — — — — — VDD_RTC — — — — — — VDD_ADC — — — — — — MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-7...
Page 218 All multiple-pin functions are listed in Table 14-3. Table 14-3. Multiple-Pin Functions Function Direction Associated Pins U2RXD I2C_SDA, DT3IN U2TXD I2C_SCL, DT2IN CANRX U0RXD, I2C_SDA, LCD_D12 CANTX UOTXD, I2C_SCL, LCD_D13 DT1IN DT1IN, U0RTS MCF52277 Reference Manual, Rev. 1 14-8 Freescale Semiconductor...
Page 219: Memory Map/Register Definition
0xFC0A_4016 PDDR_LCDDATAM 0x00 14.3.2/14-12 0xFC0A_4017 PDDR_LCDDATAL 0x00 14.3.2/14-12 Port Pin Data/Set Data Registers 0xFC0A_4018 PPDSDR_BE See Section 14.3.3/14-13 0xFC0A_4019 PPDSDR_CS See Section 14.3.3/14-13 0xFC0A_401A PPDSDR_FBCTL See Section 14.3.3/14-13 0xFC0A_401B PPDSDR_I2C See Section 14.3.3/14-13 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-9...
Page 220 0xFC0A_4033 PAR_I2C 0x00 14.3.5.4/14-18 0xFC0A_4034 PAR_UART 0x0000 14.3.5.5/14-18 0xFC0A_4036 PAR_DSPI 0x00 14.3.5.6/14-19 0xFC0A_4037 PAR_TIMER 0x00 14.3.5.7/14-20 0xFC0A_4038 PAR_LCDCTL 0x00 14.3.5.8/14-20 0xFC0A_4039 PAR_IRQ 0x00 14.3.5.9/14-21 0xFC0A_403C PAR_LCDH 0x0000_0000 14.3.5.10/14-22 0xFC0A_4040 PAR_LCDL 0x0000_0000 14.3.5.11/14-22 MCF52277 Reference Manual, Rev. 1 14-10 Freescale Semiconductor...
Page 221: Port Output Data Registers (Podr_X)
PODR_x register, clear the PODR_x bits, or clear the corresponding bits in the PCLRR_x register. Address: 0xFC0A_4005 (PODR_UART) Access: User read/write 0xFC0A_400A (PODR_LCDDATAM) 0xFC0A_400B (PODR_LCDDATAL) PODR_x Reset: Figure 14-2. Port x Output Data Registers (PODR_x) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-11...
Page 222: Port Data Direction Registers (Pddr_X)
The PDDRs are read/write. At reset, all bits in the PDDRs are cleared. Setting any bit in a PDDR_x register configures the corresponding port pin as an output. Clearing any bit in a PDDR_x register configures the corresponding pin as an input. MCF52277 Reference Manual, Rev. 1 14-12 Freescale Semiconductor...
Page 223: Port Pin Data/Set Data Registers (Ppdsdr_X)
The PPDSDR registers reflect the current pin states and control the setting of output pins when the pin is configured for GPIO. The PPDSDR_x registers are each eight bits wide, but not all ports use all eight bits. The register definitions for all ports are shown in the below figures. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-13...
Page 224 0 Port x pin state is 0 1 Port x pin state is 1 PSDR_x Port x set data bits. (write) 0 No effect. 1 Set corresponding PODR_x bit. Note: See above figures for bit field positions. MCF52277 Reference Manual, Rev. 1 14-14 Freescale Semiconductor...
Page 225: Port Clear Output Data Registers (Pclrr_X)
Figure 14-13. Port x Clear Output Data Registers (PCLRR_x) Table 14-8. PCLRR_x Field Descriptions Field Description PCLRR_x Port x clear data bits. 0 Clears corresponding PODR_x bit 1 No effect Note: See above figures for bit field positions. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-15...
Page 226: Pin Assignment Registers (Par_X)
The PAR_CS register controls the functions of the FlexBus chip select pins. After reset the byte enable signals are configured to their primary functions. Address: 0xFC0A_4031 (PAR_CS) Access: User read/write PAR_CS3 PAR_CS2 PAR_CS1 PAR_CS0 Reset: Figure 14-15. Chip Select Pin Assignment Register (PAR_CS) MCF52277 Reference Manual, Rev. 1 14-16 Freescale Semiconductor...
Page 227 0 FB_TA pin configured for GPIO 1 FB_TA pin configured for FlexBus transfer acknowledge function FB_R/W pin assignment. PAR_RWB 0 FB_R/W pin configured for GPIO 1 FB_R/W pin configured for FlexBus read/write function MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-17...
Page 228 UART Pin Assignment Register (PAR_UART) The PAR_UART register controls the functions of the UART pins. Address: 0xFC0A_4034 (PAR_UART) Access: User read/write PAR_U1CTS PAR_U1RTS PAR_U1RXD PAR_U1TXD PAR_U0CTS PAR_U0RTS PAR_U0RXD PAR_U0TXD Reset Figure 14-18. UART Pin Assignment (PAR_UART) MCF52277 Reference Manual, Rev. 1 14-18 Freescale Semiconductor...
Page 229 DSPI pin assignment. These bit fields configure the DSPI pins for one of their primary functions or GPIO. PAR_PCS0 5–4 PAR_PCS0 PAR_SIN PAR_SOUT PAR_SCK PAR_SIN GPIO GPIO GPIO GPIO 3–2 PAR_SOUT Reserved Reserved Reserved Reserved 1–0 PAR_SCK U2RTS U2RXD U2TXD U2CTS DSPI_PCS0 DSPI_SIN DSPI_SOUT DSPI_SCK MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-19...
Page 230 Reserved, must be cleared. 4–3 LCD_ACD/OE pin assignment. PAR_ACD_OE 00 LCD_ACD/OE pin configured as GPIO. 01 Reserved 10 LCD_ACD/OE pin configured for LCD_SPL_SPR function. 11 LCD_ACD/OE pin configured for LCD controller ACD/OE function. MCF52277 Reference Manual, Rev. 1 14-20 Freescale Semiconductor...
Page 231 00 IRQ1 pin configured as GPIO or external interrupt request 1 function as determined by the edge port module. Chapter 16, “Edge Port Module (EPORT),” for details. 01 IRQ1 pin configured for SSI_CLKIN function 10 IRQ1 pin configured for USB_CLKIN function 11 Reserved MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-21...
Page 232 The PAR_LCDL register controls the functions of the LCDC data pins. Address: 0xFC0A_4040 (PAR_LCDL) Access: User read/write PAR_LD11 PAR_LD10 PAR_LD9 PAR_LD8 PAR_LD7 PAR_LD6 PAR_LD5 PAR_LD4 Reset: PAR_LD3 PAR_LD2 PAR_LD1 PAR_LD0 Reset: Figure 14-24. LCD Data Low Pin Assignment (PAR_LCDL) MCF52277 Reference Manual, Rev. 1 14-22 Freescale Semiconductor...
Page 233: Flexbus Mode Select Control Register (Mscr_Flexbus)
The MSCR_FLEXBUS register controls the output mode selects of the following FlexBus pins: FB_A[23:0], FB_D[31:0], FB_BE/BWE[3:0], FB_OE, FB_R/W, FB_CS[5:0], FB_TA and FB_TS. Address: 0xFC0A_4044 (MSCR_FLEXBUS) Access: User read/write MSCR_DUPPER MSCR_DLOWER MSCR_ADDRCTL Reset: Figure 14-25. FlexBus Mode Select Control Register (MSCR_FLEXBUS) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-23...
Page 234: Sdram Mode Select Control Register (Mscr_Sdram)
MSCR_ 00 Half strength 1.8V low power/mobile DDR SDCLKB 01 Open drain 10 Full strength 1.8V low power/mobile DDR 11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays MCF52277 Reference Manual, Rev. 1 14-24 Freescale Semiconductor...
Page 235: Drive Strength Control Registers (Dscr_X)
DSE_RSTOUT DSE_FBCLK Reset: See Note Note: Reset state is dependent on the chosen reset configuration. See Chapter 9, “Chip Configuration Module (CCM),” for details. Figure 14-28. Clock/Reset Drive Strength Control Register (DSCR_CLKRST) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-25...
Page 236: Functional Description
Overview Initial pin function is determined during reset configuration. The pin assignment registers allow the user to select among various primary functions and general purpose I/O after reset. Most pins are configured MCF52277 Reference Manual, Rev. 1 14-26 Freescale Semiconductor...
Page 237: Port Digital I/O Timing
Data written to the PODR_x register of any pin configured as a general purpose output is immediately driven to its respective pin, as shown in Figure 14-31. FB_CLK Output Data Register Output Pin Figure 14-31. General Purpose Output Timing MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 14-27...
Page 238: Initialization/Application Information
The initialization for the ports module is done during reset configuration. All registers are reset to a predetermined state. Refer to Section 14.3, “Memory Map/Register Definition,” for more details on reset and initialization. MCF52277 Reference Manual, Rev. 1 14-28 Freescale Semiconductor...
Page 239: Introduction
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt acknowledge (IACK) cycle with the ColdFire implementation using a special memory-mapped address MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 15-1...
Page 240: Memory Map/Register Definition
0xFC04_C000 Global IACK Registers Space 0xFC05_4000 This address space only contains the global SWIACK and global L1ACK-L7IACK registers. See Section 15.2.10, “Software and Level 1–7 IACK Registers (SWIACKn, L1IACKn–L7IACKn)" for more information MCF52277 Reference Manual, Rev. 1 15-2 Freescale Semiconductor...
Page 241 0xFC04_C040 + n Interrupt Control Registers (ICR1n) 0x00 15.2.9/15-11 (n=1:63) 0xFC04_C0E0 Software Interrupt Acknowledge (SWIACK1) 0x00 15.2.10/15-14 0xFC04_C0E0 + 4n Level n Interrupt Acknowledge Registers (LnIACK1) 0x18 15.2.10/15-14 (n=1:7) Global IACK Registers MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 15-3...
Page 242: Interrupt Pending Registers (Iprhn, Iprln)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 15-2. Interrupt Pending Register Low (IPRLn) MCF52277 Reference Manual, Rev. 1 15-4...
Page 243: Interrupt Mask Register (Imrhn, Imrln)
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 15-3. Interrupt Mask Register High (IMRHn) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 244: Interrupt Force Registers (Intfrchn, Intfrcln)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 15-5. Interrupt Force Register High (INTFRCHn) MCF52277 Reference Manual, Rev. 1 15-6...
Page 245: Interrupt Configuration Register (Iconfign)
If round-robin arbitration is enabled, this bit has no effect. If cleared, the assertion of a level-n request does not affect the processor’s bus master priority. 8–6 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 15-7...
Page 246: Set Interrupt Mask Register (Simrn)
IMRn register to be cleared. The CIMRn[CALL] bit provides a global clear function, forcing the entire contents of IMRn to be cleared, thus enabling all interrupts. Reads of this register return all zeroes. This MCF52277 Reference Manual, Rev. 1 15-8...
Page 247: Current Level Mask Register (Clmask)
NOTE Only one copy of this register exists among the 2 interrupt controller modules. All reads and writes to this register must be made to the INTC0 memory space. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 15-9...
Page 248: Saved Level Mask Register (Slmask)
NOTE Only one copy of this register exists among the two interrupt controller modules. All reads and writes to this register must be made to the INTC0 memory space. MCF52277 Reference Manual, Rev. 1 15-10 Freescale Semiconductor...
Page 249: Interrupt Control Register (Icr0N, Icr1N, (N = 00, 01, 02, ..., 63))
7 interrupt is given the highest priority. If interrupt masking is enabled (ICONFIG[EMASK] = 1), the acknowledgement of a level-n request forces the controller to automatically mask all interrupt requests of level-n and lower. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 15-11...
Page 250: Interrupt Sources
Core Watchdog Timeout Write SCMISR[CWIC] = 1 UART0 UISR0 register UART0 Interrupt Request Automatically cleared UART1 UISR1 register UART1 Interrupt Request Automatically cleared UART2 UISR2 register UART2 Interrupt Request Automatically cleared Not Used MCF52277 Reference Manual, Rev. 1 15-12 Freescale Semiconductor...
Page 251 Write 1 to BUF13I after reading as 1 BUF14I Message Buffer 14 Interrupt Write 1 to BUF14I after reading as 1 BUF15I Message Buffer 15 Interrupt Write 1 to BUF15I after reading as 1 20–42 Not Used MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 15-13...
Page 252: Software And Level 1–7 Iack Registers (Swiackn, L1Iackn–L7Iackn)
The vector number is supplied as the data for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt controller also loads the level into the CLMASK register, where it may be retrieved later. MCF52277 Reference Manual, Rev. 1 15-14 Freescale Semiconductor...
Page 253 VECTOR pending interrupt source. A read from one of the LnIACK registers returns the highest priority unmasked interrupt source within the level. A write to any IACK register causes an error termination. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 15-15...
Page 254: Functional Description
Interrupt Vector Determination After the core has sampled for pending interrupts and begun interrupt exception processing, it generates an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a memory-mapped byte read by MCF52277 Reference Manual, Rev. 1 15-16 Freescale Semiconductor...
Page 255: Prioritization Between Interrupt Controllers
If both interrupt controllers have active interrupts at the same level, then the INTC0 interrupt ise serviced first. If INTC1 has an active interrupt with a higher level than the highest INTC0 interrupt, the INTC1 interrupt is serviced first. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 15-17...
Page 256: Low-Power Wake-Up Operation
Interrupt Service Routines This section focuses on the interaction of the interrupt masking functionality with the service routine. Figure 15-14 presents a timing diagram showing various phases during the execution of an interrupt MCF52277 Reference Manual, Rev. 1 15-18 Freescale Semiconductor...
Page 257 IACK to see if there are any pending properly-enabled requests. Checking for any pending interrupt requests at this time provides ability to initiate processing of MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 258 Obviously, there are many variations to the managing of the SR[I] and the CLMASK values to create a flexible, responsive system for managing interrupt requests within the device. MCF52277 Reference Manual, Rev. 1 15-20 Freescale Semiconductor...
Page 259: Introduction
Figure 16-1. EPORT Block Diagram NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 14, “General Purpose I/O Module”) prior to configuring the edge-port module. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 16-1...
Page 260: Low-Power Mode Operation
EPORT data register (EPDR). All bits in the EPDR are set at reset. 16.4 Memory Map/Register Definition This subsection describes the memory map and register structure. Refer to Table 16-2 for a description of the EPORT memory map. MCF52277 Reference Manual, Rev. 1 16-2 Freescale Semiconductor...
Page 261: Eport Pin Assignment Register (Eppar)
The EPORT pin assignment register (EPPAR) controls the function of each pin individually. Address: 0xFC09_4000 (EPPAR) Access: Supervisor read/write EPPA7 EPPA6 EPPA5 EPPA4 EPPA3 EPPA2 EPPA1 Reset Figure 16-2. EPORT Pin Assignment Register (EPPAR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 16-3...
Page 262: Eport Data Direction Register (Epddr)
Software can generate interrupt requests by programming the EPORT data register when the EPDDR selects output. 0 Corresponding EPORT pin configured as input 1 Corresponding EPORT pin configured as output Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 16-4 Freescale Semiconductor...
Page 263: Edge Port Interrupt Enable Register (Epier)
Edge Port Data Bits. An internal register stores data written to EPDR; if any pin of the port is configured as an output, EPDn the bit stored for that pin is driven onto the pin. Reading EDPR returns the data stored in the register. Reset sets EPD7–EPD1. Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 16-5...
Page 264: Edge Port Pin Data Register (Eppdr)
1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARn equals 00), pin transitions do not affect this register. 0 Selected edge for IRQn pin has not been detected. 1 Selected edge for IRQn pin has been detected. Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 16-6 Freescale Semiconductor...
Page 265: Overview
Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 17-1. eDMA Block Diagram MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-1...
Page 266: Features
(TCD). The minor loop is the sequence of read-write operations that transfers these NBYTES per service request. A major loop is the number of minor loop iterations defining a task. MCF52277 Reference Manual, Rev. 1 17-2 Freescale Semiconductor...
Page 267: Debug Mode
After a service request has been initiated, it cannot be cancelled. Removing a service request after it has been asserted may result in one of three actions depending on the DMA engine’s status: • The request is never recognized because another channel is executing. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-3...
Page 268: Memory Map/Register Definition
The channel priority registers assign the priorities (see Section 17.6.15, “eDMA Channel n Priority Registers (DCHPRIn)”). In round-robin arbitration mode, the channel priorities are ignored, and channels are cycled through without regard to priority. MCF52277 Reference Manual, Rev. 1 17-4 Freescale Semiconductor...
Page 269: Edma Error Status Register (Edma_Es)
The minor loop byte count must be a multiple of the source and destination transfer sizes. • All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-5...
Page 270 Address: 0xFC04_4004 (EDMA_ES) Access: User read-only R VLD Reset ERRCHN Reset Figure 17-4. eDMA Error Status Register (EDMA_ES) MCF52277 Reference Manual, Rev. 1 17-6 Freescale Semiconductor...
Page 271 1 The last recorded error was a bus error on a source read. Destination bus error. 0 No destination bus error. 1 The last recorded error was a bus error on a destination write. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-7...
Page 272: Edma Enable Request Register (Edma_Erq)
UISR1[FFULL/RXRDY] UART1 Receive UISR1[TXRDY] UART1 Transmit UISR2[FFULL/RXRDY] UART2 Receive UISR2[TXRDY] UART2 Transmit DTER0[CAP] or DTER0[REF] / Timer 0 / SSI0 Receive SSISR[RFF0] DTER1[CAP] or DTER1[REF] / Timer 1 / SSI1 Receive SSISR[RFF1] MCF52277 Reference Manual, Rev. 1 17-8 Freescale Semiconductor...
Page 273: Edma Enable Error Interrupt Registers (Edma_Eei)
Enable error interrupt n. EEIn 0 The error signal for channel n does not generate an error interrupt. 1 The assertion of the error signal for channel n generates an error interrupt request. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-9...
Page 274: Edma Set Enable Request Register (Edma_Serq)
EDMA_ERQ to be cleared, disabling all DMA request inputs. Reads of this register return all zeroes. Address: 0xFC04_4019 (EDMA_CERQ) Access: User write-only CAER CERQ Reset Figure 17-8. eDMA Clear Enable Request Register (EDMA_CERQ) MCF52277 Reference Manual, Rev. 1 17-10 Freescale Semiconductor...
Page 275: Edma Set Enable Error Interrupt Register (Edma_Seei)
EDMA_EEI to be cleared. Setting the CAEE bit provides a global clear function, forcing the EDMA_EEI contents to be cleared, disabling all DMA request inputs. Reads of this register return all zeroes. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-11...
Page 276: Edma Clear Interrupt Request Register (Edma_Cint)
Table 17-12. EDMA_CINT Field Descriptions Field Description Reserved, must be cleared. Clear all interrupt requests. CAIR 0 Clear only those EDMA_INT bits specified in the CINT field. 1 Clear all bits in EDMA_INT. MCF52277 Reference Manual, Rev. 1 17-12 Freescale Semiconductor...
Page 277: Edma Clear Error Register (Edma_Cerr)
The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. Reads of this register return all zeroes. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-13...
Page 278: Edma Clear Done Status Bit Register (Edma_Cdne)
0 Clears only those TCDn_CSR[DONE] bits specified in the CDNE field. 1 Clears all bits in TCDn_CSR[DONE] 5–4 Reserved, must be cleared. 3–0 Clear DONE bit. Clears the corresponding bit in TCDn_CSR[DONE]. CDNE MCF52277 Reference Manual, Rev. 1 17-14 Freescale Semiconductor...
Page 279: Edma Interrupt Request Register (Edma_Int)
A zero in any bit position has no affect on the corresponding channel’s current error status. The EDMA_CERR is provided so the error indicator for a single channel can easily be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-15...
Page 280: Edma Channel N Priority Registers (Dchprin)
– Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111. Figure 17-17. eDMA Channel n Priority Register (DCHPRIn) MCF52277 Reference Manual, Rev. 1 17-16 Freescale Semiconductor...
Page 281: Transfer Control Descriptors (Tcdn)
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 17-18. TCDn Source Address (TCDn_SADDR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 282 Address: 0xFC04_5006 + (0x20 × n) (TCDn_SOFF) Access: User read/write SOFF Reset — — — — — — — — — — — — — — — — Figure 17-20. TCDn Signed Source Address Offset (TCDn_SOFF) MCF52277 Reference Manual, Rev. 1 17-18 Freescale Semiconductor...
Page 283 Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 17-23. TCDn Destination Address (TCDn_DADDR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 284 Note: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. MCF52277 Reference Manual, Rev. 1 17-20 Freescale Semiconductor...
Page 285 LINKCH BITER E_LINK = 0 E_LINK BITER Reset — — — — — — — — — — — — — — — — Figure 17-27. TCDn Beginning Major Iteration Count (TCDn_BITER) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-21...
Page 286 INT_ INT_ STAR MAJOR_LINKCH DONE ACTIVE E_SG D_REQ E_LINK HALF MAJOR Reset — — — — — — — — — — — — — Figure 17-28. TCDn Control and Status (TCDn_CSR) MCF52277 Reference Manual, Rev. 1 17-22 Freescale Semiconductor...
Page 287 Disable request. If this flag is set, the eDMA hardware automatically clears the corresponding DMAERQ bit D_REQ when the current major iteration count reaches zero. 0 The channel’s DMAERQ bit is not affected. 1 The channel’s DMAERQ bit is cleared when the major loop is complete. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-23...
Page 288: Functional Description
If the major iteration count is exhausted, additional processing are performed, including the final address pointer updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation. MCF52277 Reference Manual, Rev. 1 17-24 Freescale Semiconductor...
Page 289: Edma Basic Data Flow
The TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-25...
Page 290 The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write. This source read/destination write processing continues until the minor byte count has transferred. MCF52277 Reference Manual, Rev. 1 17-26 Freescale Semiconductor...
Page 291 TCD from memory using the scatter/gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 17-31. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-27...
Page 292: Initialization/Application Information
4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the EDMA_ERQ. 6. Request channel service by software (setting the TCDn_CSR[START] bit) or hardware (slave device asserting its eDMA peripheral request signal). MCF52277 Reference Manual, Rev. 1 17-28 Freescale Semiconductor...
Page 293 DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-29...
Page 294 Current Major Loop Iteration Count (CITER) DMA Request Minor Loop DMA Request Minor Loop Major Loop DMA Request Minor Loop Table 17-33 lists the memory array terms and how the TCD settings interrelate. MCF52277 Reference Manual, Rev. 1 17-30 Freescale Semiconductor...
Page 295: Dma Programming Errors
17.8.3 DMA Arbitration Mode Considerations 17.8.3.1 Fixed Channel Arbitration In this mode, the channel service request from the highest priority channel is selected to execute. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-31...
Page 296: Dma Transfer
4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source-to-destination transfers are executed as follows: a) Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. MCF52277 Reference Manual, Rev. 1 17-32 Freescale Semiconductor...
Page 297 Write longword to location 0x2004 → second iteration of the minor loop. e) Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-33...
Page 298 MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits MCF52277 Reference Manual, Rev. 1 17-34...
Page 299: Edma Tcdn Status Monitoring
TCDn_CITER field and test for a change. The hardware request and acknowledge handshakes signals are not visible in the programmer’s model. The TCD status bits execute the following sequence for a hardware-activated channel: MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-35...
Page 300: Channel Linking
The TCDn_CITER[E_LINK] field determines whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the major loop except for the last. When the major MCF52277 Reference Manual, Rev. 1 17-36 Freescale Semiconductor...
Page 301: Dynamic Programming
This section provides recommended methods to change the programming model during channel execution. 17.8.7.1 Dynamic Channel Linking and Dynamic Scatter/Gather Dynamic channel linking and dynamic scatter/gather is the process of changing the TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits during channel execution. These bits are read MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 17-37...
Page 302 NOTE Software must clear the TCDn_CSR[DONE] bit before writing the TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits. The TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after a channel begins execution. MCF52277 Reference Manual, Rev. 1 17-38 Freescale Semiconductor...
Page 303: Introduction
ROM access and programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM and flash memories. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 304: Features
The chip-select signal indicates which device is selected. A particular chip-select asserts when the transfer address is within the device’s address space, as defined in the base- and mask-address registers (see Section 18.3, “Memory Map/Register Definition”). MCF52277 Reference Manual, Rev. 1 18-2 Freescale Semiconductor...
Page 305: Byte Enables/Byte Write Enables (Fb_Be/Bwe[3:0])
The device negates FB_CSn one cycle after the last FB_TA asserts. During read cycles, the peripheral must continue to drive data until FB_TA is recognized. For write cycles, the processor continues driving data one clock after FB_CSn is negated. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-3...
Page 306: Memory Map/Register Definition
Because the FlexBus module is one of the slaves connected to the crossbar switch, it is only accessible within a certain memory range. The only applicable address ranges for which the chip-selects can be active are 0x0000_0000–0x3FFF_FFFF and 0xC000_0000–0xDFFF_FFFF. Set the CSARn registers appropriately. MCF52277 Reference Manual, Rev. 1 18-4 Freescale Semiconductor...
Page 307: Chip-Select Mask Registers (Csmr0–Csmr5)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18-2. Chip-Select Mask Registers (CSMRn) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-5...
Page 308: Chip-Select Control Registers (Cscr0–Cscr5)
Chip-Select Control Registers (CSCR0–CSCR5) Each CSCRn, Figure 18-3, controls the auto-acknowledge, address setup and hold times, port size, burst capability, and activation of each chip-select. To support the global chip-select, FB_CS0, the CSCR0 reset MCF52277 Reference Manual, Rev. 1 18-6 Freescale Semiconductor...
Page 309 01 Assert FB_CSn on second rising clock edge after address is asserted. 10 Assert FB_CSn on third rising clock edge after address is asserted. 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-7...
Page 310 Note: If AA is set for a corresponding FB_CSn and the external system asserts an external FB_TA before the wait-state countdown asserts the internal FB_TA, the cycle is terminated. Burst cycles increment the address bus between each internal termination. MCF52277 Reference Manual, Rev. 1 18-8 Freescale Semiconductor...
Page 311: Functional Description
Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, address setup and hold times, and automatic acknowledge generation features. See Section 18.3.3, “Chip-Select Control Registers (CSCR0–CSCR5).” FB_CS0 is a global chip-select after reset and provides re-locatable boot ROM capability. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-9...
Page 312: Data Transfer Operation
The address, write data, FB_TS, FB_CSn, and all attribute signals change on the rising edge of the clock. Read data is latched into the device on the rising edge of the clock. MCF52277 Reference Manual, Rev. 1 18-10 Freescale Semiconductor...
Page 313: Data Byte Alignment And Physical Connections
4. S3: FB_CSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes, and write data. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 314: Flexbus Timing Examples
18.4.5 FlexBus Timing Examples NOTE Because this device shares the FlexBus signals with the SDRAM controller, all signals, except the chip selects, tristate between bus cycles. MCF52277 Reference Manual, Rev. 1 18-12 Freescale Semiconductor...
Page 315: Basic Read Bus Cycle
The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the read bus cycles the address signals are indeterminate. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-13...
Page 316: Basic Write Bus Cycle
FlexBus asserts internal FB_TA (auto acknowledge/internal termination). 2. Latch data on FB_D[31:X]. Sample FB_TA low. Assert FB_TA (external termination). 1. Negate FB_TA (external termination). 1. Start next cycle. Figure 18-8. Write-Cycle Flowchart MCF52277 Reference Manual, Rev. 1 18-14 Freescale Semiconductor...
Page 317 The external device returns the read data on FB_D[31:24] and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. FB_CLK FB_A[23:0] ADDR[23:0] ADDR[31:24] FB_D[31:24] DATA[7:0] FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB_TA Figure 18-10. Single Byte-Read Transfer MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-15...
Page 318 FB_D[31:16], and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. FB_CLK FB_A[23:0] ADDR[23:0] ADDR[31:16] FB_D[31:16] DATA[15:0] FB_R/W FB_TS FB_CSn, FB_OE FB_BE/BWEn FB_TA Figure 18-12. Single Word-Read Transfer MCF52277 Reference Manual, Rev. 1 18-16 Freescale Semiconductor...
Page 319 FB_TA Figure 18-13. Single Word-Write Transfer Figure 18-14 depicts a longword read through a 32-bit device. FB_CLK FB_A[23:0] ADDR[23:0] ADDR[31:0] FB_D[31:0] DATA[31:0] FB_R/W FB_TS FB_CSn, FB_OE FB_BE/BWEn FB_TA Figure 18-14. Longword-Read Transfer MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-17...
Page 320: Timing Variations
Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states can give the peripheral or memory more time to return read data or sample write data. MCF52277 Reference Manual, Rev. 1 18-18...
Page 321 FB_CSn, FB_OE, FB_BE/BWEn FB_TA Figure 18-16. Basic Read-Bus Cycle (No Wait States) FB_CLK FB_A[23:0] ADDR[23:0] FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA Figure 18-17. Basic Write-Bus Cycle (No Wait States) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-19...
Page 322 The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis. Each chip-select can be programmed to assert one to four clocks after MCF52277 Reference Manual, Rev. 1 18-20...
Page 323 Figure 18-20. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) FB_CLK FB_A[23:0] ADDR[23:0] FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA Figure 18-21. Write-Bus Cycle with Two Clock Address Setup (No Wait States) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-21...
Page 324 Figure 18-22. Read Cycle with Two-Clock Address Hold (No Wait States) FB_CLK FB_A[23:0] ADDR[23:0] FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA Figure 18-23. Write Cycle with Two-Clock Address Hold (No Wait States) MCF52277 Reference Manual, Rev. 1 18-22 Freescale Semiconductor...
Page 325: Burst Cycles
The CSCRn registers enable bursting for reads, writes, or both. Memory spaces can be declared burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW] bits. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-23...
Page 326 ADDR + 1 ADDR + 2 ADDR + 3 ADDR FB_D[31:24] DATA DATA DATA DATA [31:24] FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB_TA Figure 18-26. Longword-Write Burst to 8-Bit Port 3-1-1-1 (No Wait States) MCF52277 Reference Manual, Rev. 1 18-24 Freescale Semiconductor...
Page 327 ADDR + 1 ADDR + 2 ADDR + 3 ADDR FB_D[31:24] DATA DATA DATA DATA DATA [31:24] FB_R/W FB_TS FB_CSn FB_BE/BWEn FB_OE FB_TA Figure 18-28. Longword-Write Burst-Inhibited to 8-Bit Port (No Wait States) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-25...
Page 328 ADDR + 1 ADDR + 2 ADDR + 3 ADDR FB_D[31:24] DATA DATA DATA DATA [31:24] FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB_TA Figure 18-30. Longword-Write Burst to 8-Bit Port 3-2-2-2 (One Wait State) MCF52277 Reference Manual, Rev. 1 18-26 Freescale Semiconductor...
Page 329: Misaligned Operands
FB_TA Figure 18-32. Longword-Write Burst to 8-Bit Port 3-1-1-1 (Address Setup and Hold) 18.4.7 Misaligned Operands Because operands, unlike opcodes, can reside at any byte boundary, they are allowed to be misaligned. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 18-27...
Page 330: Bus Errors
FB_TA when the bus error occurs can invoke an interrupt handler. The device also includes a bus monitor that generates a bus error for unterminated cycles. MCF52277 Reference Manual, Rev. 1 18-28 Freescale Semiconductor...
Page 331: Introduction
SDRAM controller and the FlexBus module. However, when the SDRAM controller is in DDR mode, D[31:16] is dedicated to the SDRAM data bus and D[15:0] is dedicated to the FlexBus data bus. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-1...
Page 332: Block Diagram
24 in 32-bit bus mode or 25 in 16-bit bus mode. • Minimum memory configuration of 8 MByte — 11 bit row address (RA), 8 bit column address (CA), 2 bit bank address (BA), 32-bit bus, one chip select MCF52277 Reference Manual, Rev. 1 19-2 Freescale Semiconductor...
Page 333: Terminology
O Memory bank address. Define which bank an , or PRECHARGE command is being ACTV READ WRITE applied. It is also used to select the SDRAM internal mode register during power-up initialization. Timing Assertion/Negation — Occurs synchronously with SD_CLK MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-3...
Page 334 SD_DM2 - SD_D[23:16] SD_DM1 - SD_D[15:8] SD_DM0 - SD_D[7:0] State Asserted — Data is written to SDRAM Meaning Negation — Data is masked Timing Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK. MCF52277 Reference Manual, Rev. 1 19-4 Freescale Semiconductor...
Page 335: Interface Recommendations
SDRAM’s data bus. For example, if 16-bit wide devices are used, then user must use two 16-bit devices connected as a 32-bit port. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-5...
Page 336 14 x 8 x 4 — — RA13 RA12 12 x 11 x 4 — CA11 32M x 4 bit 13 x 10 x 4 — RA12 14 x 9 x 4 — RA13 RA12 MCF52277 Reference Manual, Rev. 1 19-6 Freescale Semiconductor...
Page 337 All SD_A[13:0] bits are generated on every access, but only the bits actually used by the memory are shown. All column address (CA) bits in this table are physical column address lines. The SDRAM controller inserts an extra bit CA10 to control the precharge option. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-7...
Page 338 — — RA13 RA12 12 x 12 x 4 — CA12 CA11 64M x 4 bit 13 x 11 x 4 — CA11 RA12 14 x 10 x 4 — RA13 RA12 MCF52277 Reference Manual, Rev. 1 19-8 Freescale Semiconductor...
Page 339 If all devices’ column address width is 9 bits, the row address can be ≥ 11 bits. • • The maximum row bits plus column bits equals 25. • x16 data width memory devices cannot be mixed with any other width. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-9...
Page 340: Sdram Sdr Connections
This aligns SD_SDRDQS to the SD_CLK as if the memory had generated the DQS pulse. The inbound trace should be routed along the data path, which should synchronize the SD_DQS so that the data is latched in the middle of the data valid window. MCF52277 Reference Manual, Rev. 1 19-10 Freescale Semiconductor...
Page 341 SD_CS0 SD_RAS SD_CAS SDWE SD_A10 A10/AP SD_SDR_DQS Delay SD_DQS[3:2] SD_DQM[3:0] DQM[3:0] A[15:14] BA[1:0] SD_A[23:0] A[13:11,9:0] A[13:11,9:0] SD_D[31:0] D[31:0] 3.3V Flash A[23:2] A[21:0] D[31:0] FB_CS0 Figure 19-2. Example 3.3V, 32-bit SDR SDRAM System MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-11...
Page 342: Sdram Ddr Component Connections
Figure 19-3. Example 2.5V, 16-bit DDR SDRAM System 19.3.4 DDR SDRAM Layout Considerations Due to the critical timing for DDR SDRAM, a number of considerations should be taken into account during PCB layout: • Minimize overall trace lengths. MCF52277 Reference Manual, Rev. 1 19-12 Freescale Semiconductor...
Page 343: Termination Example
Address, Data Address, Data and Control and Control SD_CLK 100 Ω Note: Place 100 Ω resistor as close as possible to the DDR’s clock receiver SD_CLK Figure 19-4. DDR SDRAM Termination Circuit MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-13...
Page 344: Memory Map/Register Definition
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-5. SDRAM-Mode/Extended-Mode Register (SDMR) MCF52277 Reference Manual, Rev. 1 19-14 Freescale Semiconductor...
Page 345: Sdram Control Register (Sdcr)
Clock enable. CKE must be set to perform normal read and write operations. Clear CKE to put the memory in self-refresh or power-down mode. 0 SD_CKE is negated (low) 1 SD_CKE is asserted (high) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-15...
Page 346 32-bit DDR devices have only a single DQS pin. Enable one of the SD_DQSn signals and disable the other. Then, short both pins external to the device. 1 SD_DQSn can drive as necessary, depending on commands and SDCR[OE_RULE] setting. DDR only. 9–3 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 19-16 Freescale Semiconductor...
Page 347: Sdram Configuration Register 1 (Sdcfg1)
SD_CLK2—double frequency of SD_CLK—DDR uses both edges of the bus-frequency clock (SD_CLK) to read/write data NOTE In all calculations for setting the fields of this register, convert time units to clock units and round up to the nearest integer. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-17...
Page 348 = 99 MHz SD_CLK Suggested value = (20ns × 99 MHz) - 1= 0.98; round to 1. Note: Count value is in SD_CLK periods for SDR and DDR modes. Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 19-18 Freescale Semiconductor...
Page 349: Sdram Configuration Register 2 (Sdcfg2)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-8. SDRAM Configuration Register 2 (SDCFG2) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 350: Sdram Chip Select Configuration Registers (Sdcsn)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-9. SRAM Chip Select Configuration Register (SDCSn) MCF52277 Reference Manual, Rev. 1 19-20...
Page 351: Functional Description
Functional Description 19.5.1 SDRAM Commands When an internal bus master accesses SDRAM address space, the memory controller generates the corresponding SDRAM command. Table 19-12 lists SDRAM commands supported by the memory controller. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-21...
Page 352 ACTV followed by the read command. If the address is not within the active row of an active bank, the memory controller issues a pre command to close the active MCF52277 Reference Manual, Rev. 1 19-22...
Page 353 The memory controller issues the precharge command only when necessary for one of these conditions: • Access to a new row • Refresh interval elapsed • Software commanded precharge during device initialization MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-23...
Page 354 Else Reserved A6–A4 CAS latency. Delay in clocks from issuing a to valid data out. Check the SDRAM manufacturer’s spec READ because the CL settings supported can vary from memory to memory. MCF52277 Reference Manual, Rev. 1 19-24 Freescale Semiconductor...
Page 355 After REF command, the SDRAM is in an idle state and waits for an command. ACTV MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-25...
Page 356: Initialization/Application Information
The SDCR[REF and IREF] bits should remain cleared for this step. 7. Initialize the SDRAM’s extended mode register to enable the DLL. See Section 19.5.1.6, “Load Mode/Extended Mode Register Command (lmr, lemr),” for instructions on issuing a LEMR command. MCF52277 Reference Manual, Rev. 1 19-26 Freescale Semiconductor...
Page 357: Page Management
ACTV A page is kept open until one of the following conditions occurs: • An access outside the open page. • A refresh cycle is started. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 19-27...
Page 358: Transfer Size
The burst size and transfer order must be programmed in the SDRAM mode registers during initialization; the burst size also must be programmed in the memory controller (SDCFG2 register). MCF52277 Reference Manual, Rev. 1 19-28 Freescale Semiconductor...
Page 359: Introduction
USB host must disable the port and remove power. USB VBUS is not provided on-chip. This processor provides pins for control and status to an external IC capable of managing the VBUS downstream supply. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-1...
Page 360: Block Diagram
Capacitor Figure 20-1. USB On-The-Go with on-chip FS/LS Transceiver Interface Block Diagram 20.1.3 Features The USB On-The-Go module includes these features: • Complies with USB specification rev 2.0 • USB host mode MCF52277 Reference Manual, Rev. 1 20-2 Freescale Semiconductor...
Page 361: Modes Of Operation
USB enabled, low-power modes. See Section 20.1.4.1, “Low-Power Modes,” for details. 20.1.4.1 Low-Power Modes The USB OTG module is integrated with the processor’s low-power modes (stop, doze and wait). The modes are implemented as follows: MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-3...
Page 362: External Signal Description
USB OTG module must be able to individually enable and disable the pull-up and pull-down resistors on DP and DM, and it must be able to control and sense the levels on the USB VBUS line. MCF52277 Reference Manual, Rev. 1 20-4...
Page 363 Indicates valid operating level on VBUS from USB device’s perspective. Session End SEND Indicates VBUS fell below the session valid threshold. Wake-up Event WKUP Reflects when a wake-up event occurred on the USB bus. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-5...
Page 364: Memory Map/Register Definition
20.3.2.2/20-12 Capability Registers 0xFC0B_0100 Host Interface Version Number (HCIVERSION) 0x0100 20.3.3.1/20-13 0xFC0B_0103 Capability Register Length (CAPLENGTH) 0x40 20.3.3.2/20-13 0xFC0B_0104 Host Structural Parameters (HCSPARAMS) 0x0001_0011 20.3.3.3/20-14 0xFC0B_0108 Host Capability Parameters (HCCPARAMS) 0x0000_0006 20.3.3.4/20-15 MCF52277 Reference Manual, Rev. 1 20-6 Freescale Semiconductor...
Page 365 R/W 0x0000_0000 20.3.4.22/20-43 0xFC0B_01CC Endpoint Control Register 3 (EPCR3) R/W 0x0000_0000 20.3.4.22/20-43 Indicates if the register is present in the EHCI specification. Indicates if the register is available in host and/or device modes. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-7...
Page 366: Module Identification Registers
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 Figure 20-3. General Hardware Parameters Register (HWGENERAL) MCF52277 Reference Manual, Rev. 1 20-8 Freescale Semiconductor...
Page 367 Indicates number of ports in host mode minus 1. Always 0 for the USB OTG module. NPORT Indicates module is host capable. Always set. 20.3.1.4 Device Hardware Parameters Register (HWDEVICE) Provides device hardware parameters for this implementation of the USB OTG module. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-9...
Page 368 Transmit address. Number of address bits for the entire TX buffer. Always 0x06. TXADD 7–0 Transmit burst. Indicates number of data beats in a burst for transmit DMA data transfers. Always 0x04. TXBURST MCF52277 Reference Manual, Rev. 1 20-10 Freescale Semiconductor...
Page 369: Device/Host Timer Registers
GPTLD time in microseconds minus 1 for the timer duration. For example, for a one millisecond timer, load 1000 – 1 = 999 (0x00_03E7). Note: Maximum value of 0xFF_FFFF or 16.777215 seconds. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-11...
Page 370: Capability Registers
Specifies software limits, restrictions, and capabilities of the host/device controller implementation. Most of these registers are defined by the EHCI specification. Registers not defined by the EHCI specification are noted in their descriptions. MCF52277 Reference Manual, Rev. 1 20-12 Freescale Semiconductor...
Page 371 USBCMD register. Address: 0xFC0B_0103 (CAPLENGTH) Access: User read-only CAPLENGTH Reset: Figure 20-11. Capability Registers Length Register (CAPLENGTH) Table 20-14. CAPLENGTH Field Descriptions Field Description 7–0 Capability registers length. Always 0x40. CAPLENGTH MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-13...
Page 372 Number of ports. Indicates number of physical downstream ports implemented for host applications. Field value N_PORTS determines how many addressable port registers in the operational register. For the USB OTG module, this is always 0x1. MCF52277 Reference Manual, Rev. 1 20-14 Freescale Semiconductor...
Page 373 The most-significant byte of the register represents a major revision and the least-significant byte is the minor revision. Address: 0xFC0B_0120 (DCIVERSION) Access: User read-only DCIVERSION Reset Figure 20-14. Device Controller Interface Version Register (DCIVERSION) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-15...
Page 374: Operational Registers
4–0 Device endpoint number. This field indicates the number of endpoints built into the device controller. Always 0x04. 20.3.4 Operational Registers Comprised of dynamic control or status registers and are defined below. MCF52277 Reference Manual, Rev. 1 20-16 Freescale Semiconductor...
Page 375 Reserved, must be cleared. Asynchronous schedule park mode enable. Software uses this bit to enable or disable park mode. ASPE 1 Park mode enabled 0 Park mode disabled Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-17...
Page 376 001 512 elements (2048 bytes) 010 256 elements (1024 bytes) 011 128 elements (512 bytes) 100 64 elements (256 bytes) 101 32 elements (128 bytes) 110 16 elements (64 bytes) 111 8 elements (32 bytes) MCF52277 Reference Manual, Rev. 1 20-18 Freescale Semiconductor...
Page 377 Software clears certain bits in this register by writing a 1 to them. Address: 0xFC0B_0144 (USBSTS) Access: User read/write NAKI Reset Reset Figure 20-17. USB Status Register (USBSTS) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-19...
Page 378 USBCMD[PSE] bit have the same value, the periodic schedule is enabled or disabled. Used only in host mode. 0 Disabled. 1 Enabled. Reclamation. DetectS an empty asynchronous schedule. Used only by the host mode. 0 Non-empty asynchronous schedule. 1 Empty asynchronous schedule. MCF52277 Reference Manual, Rev. 1 20-20 Freescale Semiconductor...
Page 379 (as programmed in the USBCMD[FS] field) is 1024, the frame index register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the controller sets this bit each time FRINDEX[12] toggles. Used only in the host mode. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-21...
Page 380 (even if the USBINTR register disables them), allowing polling of interrupt events by the software. Address: 0xFC0B_0148 (USBINTR) Access: User read/write TIE1 TIE0 UPIE UAIE NAKE Reset Reset Figure 20-18. USB Interrupt Enable Register (USBINTR) MCF52277 Reference Manual, Rev. 1 20-22 Freescale Semiconductor...
Page 381 0 Disabled 1 Enabled System error enable. When this bit and the USBSTS[SEI] bit are set, controller issues an interrupt. Software clearing the USBSTS[SEI] bit acknowledges the interrupt. 0 Disabled 1 Enabled MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-23...
Page 382 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20-19. Frame Index Register (FRINDEX) MCF52277 Reference Manual, Rev. 1 20-24...
Page 383 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20-20. Periodic Frame List Base Address Register (PERIODICLISTBASE) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 384 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20-22. Current Asynchronous List Address Register (ASYNCLISTADDR) MCF52277 Reference Manual, Rev. 1 20-26...
Page 385 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20-24. Host TT Asynchronous Buffer Control (TTCTRL) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 386 = Time to send data payload = Total packet flight time (send-only) packet (T = Time to fetch packet into TX FIFO up to specified level = Total packet time (fetch and send) packet (T MCF52277 Reference Manual, Rev. 1 20-28 Freescale Semiconductor...
Page 387 This value is ignored if the USBMODE[SDIS] bit is set. When the USBMODE[SDIS] bit is set, the host controller behaves as if TXFIFOTHRES is set to its maximum value. 15–13 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-29...
Page 388 The USB module contains a single PORTSC register. This register only resets when power is initially applied or in response to a controller reset. Initial conditions of a port are: • No device connected • Port disabled MCF52277 Reference Manual, Rev. 1 20-30 Freescale Semiconductor...
Page 389 FS configurations with a HS host, hub, or device. Not defined in the EHCI specification. 0 Allow the port to identify itself as high speed. 1 Force the port to only connect at full speed. This bit is for debugging purposes. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-31...
Page 390 When an over-current condition is detected on a powered port, the host controller driver from a 1to a 0 (removing power from the port) transitions the PP bit in each affected port. MCF52277 Reference Manual, Rev. 1 20-32 Freescale Semiconductor...
Page 391 If host software sets this bit when the port is not enabled (PE = 0), the results are undefined. This field is cleared if the PP bit is cleared in host mode. Device mode: In device mode, this bit is a read-only status bit. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-33...
Page 392 When the port is disabled, downstream propagation of data is blocked except for reset. This field is cleared if the PP bit is cleared in host mode. Device mode: The device port is always enabled. (This bit is set). MCF52277 Reference Manual, Rev. 1 20-34 Freescale Semiconductor...
Page 393 Address: 0xFC0B_01A4 (OTGSC) Access: User read/write DPIS 1MSS BSEIS BSVIS ASVIS AVVIS IDIS DPIE 1MSE BSEIE BSVIE ASVIE AVVIE IDIE Reset DPS 1MST BSE IDPU Reset Figure 20-29. On-the-Go Status and Control Register (OTGSC) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-35...
Page 394 USB ID interrupt status. Indicates when a change on the ID input is detected. Software must write a 1 to clear this IDIS bit. Reserved, must be cleared. Data bus pulsing status. 0 No pulsing on port. 1 Pulsing detected on port. MCF52277 Reference Manual, Rev. 1 20-36 Freescale Semiconductor...
Page 395 VBUS discharge. Setting this bit causes VBUS to discharge through a resistor. 20.3.4.15 USB Mode Register (USBMODE) This register is not defined in the EHCI specification. It controls the operating mode of the module. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-37...
Page 396 Setup lockout mode. For the module in device mode, this bit controls behavior of the setup lock mechanism. See SLOM Section 20.5.3.4.4, “Control Endpoint Operation.” 0 Setup lockouts on. 1 Setup lockouts off (software requires use of the USBCMD[SUTW] bit). MCF52277 Reference Manual, Rev. 1 20-38 Freescale Semiconductor...
Page 397 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20-32. Endpoint Initialization Register (EPPRIME) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 398 FERB[3] corresponds to endpoint 3. 20.3.4.19 Endpoint Status Register (EPSR) This register is not defined in the EHCI specification. This register is only used in device mode. MCF52277 Reference Manual, Rev. 1 20-40 Freescale Semiconductor...
Page 399 If the corresponding IOC bit is set in the transfer descriptor, this bit is set simultaneously with the USBINT. Writing a 1 clears the corresponding bit in this register. ETCE[3] (bit 19) corresponds to endpoint 3. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-41...
Page 400 Reserved, must be cleared. RX endpoint enable. Endpoint zero is always enabled. 1 Enabled. 6–4 Reserved, must be cleared. 3–2 RX endpoint type. Endpoint zero is always a control endpoint. 00 Control MCF52277 Reference Manual, Rev. 1 20-42 Freescale Semiconductor...
Page 401 TX data toggle inhibit. This bit is used only for test and should always be written as 0. Writing a 1 to this bit causes this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet. 0 PID sequencing enabled. 1 PID sequencing disabled. Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-43...
Page 402 Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host. It continues returning STALL until software clears this bit or automatically clears as above, 0 Endpoint OK 1 Endpoint stalled MCF52277 Reference Manual, Rev. 1 20-44 Freescale Semiconductor...
Page 403: Functional Description
The USB module defaults to FS XCVR operation and can communicate in LS. Due to pin-count limitations the USB module only supports certain combinations of PHY interfaces and USB functionality. Refer to the Table 20-42 for more information. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-45...
Page 404: Initialization/Application Information
Host Controller Initialization After initial power-on or module reset (via the USBCMD[RST] bit), all of the operational registers are at default values, as illustrated in the register memory map in Table 20-4. MCF52277 Reference Manual, Rev. 1 20-46 Freescale Semiconductor...
Page 405: Device Data Structures
20-38, there are two endpoint queue heads in the array for each device endpoint—one for IN and one for OUT. The EPLISTADDR provides a pointer to the first entry in the array. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-47...
Page 406 While a packet is in progress, the overlay area of the dQH acts as a staging area for the dTD so the device controller can access needed information with minimal latency. Figure 20-39 shows the endpoint queue head structure. MCF52277 Reference Manual, Rev. 1 20-48 Freescale Semiconductor...
Page 407 01 Execute 1 Transaction. 10 Execute 2 Transactions. 11 Execute 3 Transactions. Note: Non-ISO endpoints must set Mult equal to 00. ISO endpoints must set Mult equal to 01, 10, or 11 as needed. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-49...
Page 408 Until a transfer expires, software must not write the queue head overlay area or the associated transfer descriptor. When the transfer is complete, the device controller writes the results back to the original transfer descriptor and advance the queue. MCF52277 Reference Manual, Rev. 1 20-50 Freescale Semiconductor...
Page 409 Figure 20-40. Endpoint Transfer Descriptor (dTD) 20.5.2.2.1 Next dTD Pointer (Offset = 0x0) The next dTD pointer is used to point the device controller to the next dTD in the linked list. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-51...
Page 410 For OUT transfers the total bytes must be evenly divisible by the maximum packet length. Interrupt on complete. Indicates if USBSTS[UI] is set in response to device controller finished with this dTD. 14–12 Reserved. Reserved for future use and must be cleared. MCF52277 Reference Manual, Rev. 1 20-52 Freescale Semiconductor...
Page 411 Current Offset 1;10–0 Frame Number. Written by the device controller to indicate the frame number a packet finishes in. Typically Frame Number correlates relative completion times of packets on an ISO endpoint. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-53...
Page 412: Device Operation
It is not necessary to initially prime endpoint 0 because the first packet received is always a setup packet. The contents of the first setup packet requires a response in accordance with USB device framework command set. MCF52277 Reference Manual, Rev. 1 20-54 Freescale Semiconductor...
Page 413 Bus Activity Software-only state Figure 20-41. USB 2.0 Device States States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the USB OTG, and they are communicated to the DCD using these status bits: MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-55...
Page 414 DCD processes a USB reset event, it is likely w3a4no dTDs have been allocated. 6. At this time, the DCD may release control back to the OS because no further changes to the device controller are permitted until a port change detect is indicated. MCF52277 Reference Manual, Rev. 1 20-56 Freescale Semiconductor...
Page 415 (one more devices) back to the active condition. NOTE Before use of resume signaling, the host must enable it by using the set feature command defined in chapter 9 Device Framework of the USB 2.0 specification. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-57...
Page 416 1 Synchronize the data PIDs Data Toggle Inhibit (TXI, RXI) 0 PID sequencing disabled Endpoint Type (TXT, RXT) 00 Control 01 Isochronous 10 Bulk 11 Interrupt Endpoint Stall (TXS, RXS) 0 Not stalled MCF52277 Reference Manual, Rev. 1 20-58 Freescale Semiconductor...
Page 417 The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by setting the data toggle reset bit in the EPCRn register. This should only happen when configuring/initializing an endpoint or returning from a STALL condition. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-59...
Page 418 After a priming request is complete, an endpoint state of primed is indicated in the EPSR register. For a primed transmit endpoint, the device controller can respond to an IN request from the host and meet the stringent bus turnaround time of high-speed USB. MCF52277 Reference Manual, Rev. 1 20-60 Freescale Semiconductor...
Page 419 Table 20-53. Variable Length Transfer Protocol Example (ZLT=1) Bytes Max. Packet (dTD) Length (dQH) — — — — NOTE The MULT field in the dQH must be set to 00 for bulk, interrupt, and control endpoints. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-61...
Page 420 Table 20-54. Interrupt/Bulk Endpoint Bus Response Matrix Token Stall Primed Underflow Overflow Type Primed Ignore Ignore Ignore Setup STALL Transmit BS Error STALL Receive + NYET/ACK STALL Ping Ignore Ignore Ignore Ignore Ignore Invalid Force bit stuff error MCF52277 Reference Manual, Rev. 1 20-62 Freescale Semiconductor...
Page 421 If a new setup packet is indicated after the EPPRIME bit is cleared, then the transfer descriptor can be freed and the DCD must re-interpret the setup packet. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-63...
Page 422 Isochronous endpoints used for real-time scheduled delivery of data, and their operational model is significantly different than the host throttled bulk, interrupt, and control data pipes. Real time delivery by the USB OTG is accomplished by: • Exactly MULT packets per (micro)frame are transmitted/received. MCF52277 Reference Manual, Rev. 1 20-64 Freescale Semiconductor...
Page 423 • TX packet retired: — MULT counter reaches zero. — Fulfillment error (transaction error bit is set): – # packets occurred > 0 AND # packets occurred < MULT MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-65...
Page 424 SOF for packet N is received. Isochronous Endpoint Bus Response Matrix Table 20-56. Isochronous Endpoint Bus Response Matrix Token Stall Primed Underflow Overflow Type Primed STALL STALL STALL Setup NULL NULL Transmit BS Error Packet Packet MCF52277 Reference Manual, Rev. 1 20-66 Freescale Semiconductor...
Page 425 The next section includes demonstration of complete initialization of the dQH including these fields. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-67...
Page 426 4. Decoding setup packet and prepare data phase (optional) and status phase transfer as required by the USB specification chapter 9 or application specific protocol. MCF52277 Reference Manual, Rev. 1 20-68 Freescale Semiconductor...
Page 427 6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer. 7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointers. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-69...
Page 428 Active = 0, Halted = 0, Transaction error = 0, Data buffer error = 0 Should any combination other than the one shown above exist, the DCD must take proper action. Transfer failure mechanisms are indicated in Section 20.5.3.6.6, “Device Error Matrix.” MCF52277 Reference Manual, Rev. 1 20-70 Freescale Semiconductor...
Page 429 ISO Fulfillment Error Both The device controller manages all errors on bulk/control/interrupt endpoints except for a data buffer overflow. However, for ISO endpoints, errors packets are not retried and errors are tagged as indicated. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-71...
Page 430: Servicing Interrupts
Table 20-60. Low Frequency Interrupt Events Interrupt Action Port Change Change software state information. Sleep Enable (Suspend) Change software state information. Low power managing as necessary. Reset Received Change software state information. Abort pending transfers. MCF52277 Reference Manual, Rev. 1 20-72 Freescale Semiconductor...
Page 431: Deviations From The Ehci Specifications
These additions to the capability registers support the embedded Transaction translator function: • N_TT added to HSCPARAMS - Host Controller Structural Parameters • N_PTT added to HSCPARAMS - Host Controller Structural Parameters MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-73...
Page 432 It is demonstrated here how hub address and endpoint speed fields should be set for directly attached FS/LS devices and hubs: 1. QH (for direct attach FS/LS) – asynchronous (bulk/control endpoints) periodic (interrupt) • Hub address equals 0 • Transactions to direct attached device/hub. MCF52277 Reference Manual, Rev. 1 20-74 Freescale Semiconductor...
Page 433 H-frame and B-frame boundaries with the exception that an asynchronous transfer cannot babble through the SOF (start of B-frame 0.) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-75...
Page 434 – Idle for more than 4 microframes — Abort of pending complete-splits – EOF – Idle for more than 4 microframes • USB 2.0 - 11.18.[7-8] — Transaction tracking for up to 4 data pipes. MCF52277 Reference Manual, Rev. 1 20-76 Freescale Semiconductor...
Page 435 Starts of microframes are timed precisely to 125 µs using the transceiver clock as a reference clock or a 60 Mhz transceiver clock for 8-bit physical interfaces and full-speed serial interfaces. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 20-77...
Page 436 A 1-bit high-speed indicator bit has been added to PORTSCn to signify that the port is in HS vs. FS/LS. — This information is redundant with the 2-bit port speed indicator field above. MCF52277 Reference Manual, Rev. 1 20-78 Freescale Semiconductor...
Page 437: Introduction
CSTN To Panel Figure 21-1. LCDC Block Diagram 21.1.2 Features The LCDC provides the following features: • Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD panels MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-1...
Page 438 Logical operation between color hardware cursor and background • Hardware panning (soft horizontal scrolling) • 8-bit pulse-width modulator for software contrast control • Graphic window support for viewfinder function in color display MCF52277 Reference Manual, Rev. 1 21-2 Freescale Semiconductor...
Page 439: External Signal Description
0xFC0A_C000 Screen Start Address Register (LCD_SSAR) 0x0000_0000 21.3.1/21-4 0xFC0A_C004 LCD Size Register (LCD_SR) 0x0000_0000 21.3.2/21-5 0xFC0A_C008 LCD Virtual Page Width Register (LCD_VPW) 0x0000_0000 21.3.3/21-5 0xFC0A_C00C LCD Cursor Position Register (LCD_CPR) 0x0000_0000 21.3.4/21-6 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-3...
Page 440: Lcdc Screen Start Address Register (Lcd_Ssar)
— 21.3.25/21-26 0xFC0A_CBFC 0xFC0A_CC00 Graphic Window Look-up Table (GWLUT) — 21.3.25/21-26 0xFC0A_CFFC 21.3.1 LCDC Screen Start Address Register (LCD_SSAR) The screen start address register specifies the start address of the LCD screen. MCF52277 Reference Manual, Rev. 1 21-4 Freescale Semiconductor...
Page 441: Lcdc Size Register (Lcd_Sr)
Note: The maximum supported panel size is 800x600 pixels. Therefore the maximum value for this bit field is 0x258. 21.3.3 LCDC Virtual Page Width Register (LCD_VPW) The virtual page width register defines the width of the virtual page for the LCD panel. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-5...
Page 442: Lcdc Cursor Position Register (Lcd_Cpr)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-5. LCD Cursor Position Register (LCD_CPR) MCF52277 Reference Manual, Rev. 1 21-6...
Page 443: Lcdc Cursor Width Height And Blink Register (Lcd_Cwhb)
0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Figure 21-6. LCD Cursor Width Height and Blink Register (LCD_CWHB) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 444: Lcdc Color Cursor Mapping Register (Lcd_Ccmr)
Table 21-9. LCD_CCMR Field Descriptions Field Description 30–18 Reserved, must be cleared. 17–12 Cursor red field. Defines the red component of the cursor color in color mode. CUR_COL_R 0x00 No red. 0x3F Full red. MCF52277 Reference Manual, Rev. 1 21-8 Freescale Semiconductor...
Page 445: Lcdc Panel Configuration Register (Lcd_Pcr)
The panel configuration register defines all of the properties of the LCD screen. Address: 0xFC0A_C018 (LCD_PCR) Access: User read/write SCLK END_ SWAP_ REV_ PBSIZ BPIX IDLE Reset R ACD SCLK SHARP Reset Figure 21-8. LCD Panel Configuration Register (LCD_PCR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-9...
Page 446 SWAP_SEL = 1. Pixel polarity. PIXPOL 0 Active high 1 Active low First line marker polarity. FLMPOL 0 Active high 1 Active low Line pulse polarity. LPPOL 0 Active high 1 Active low MCF52277 Reference Manual, Rev. 1 21-10 Freescale Semiconductor...
Page 447 Note: The value of PCD must be set such that the LCD_LSCLK frequency is at least one-third (TFT mode) or one-fourth (CSTN mode) of the peripheral bus clock (f ) frequency. Otherwise, the line data (LCD_D) sys/2 is incorrect. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-11...
Page 448: Lcdc Horizontal Configuration Register (Lcd_Hcr)
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-10. LCD Vertical Configuration Register (LCD_VCR) MCF52277 Reference Manual, Rev. 1 21-12...
Page 449: Lcdc Panning Offset Register (Lcd_Por)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-11. LCD Panning Offset Register (LCD_POR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 450: Lcdc Sharp Configuration Register (Lcd_Scr)
LCD_PS rise delay. Controls the delay of the rising edge of LCD_PS relative to the falling edge of LCD_CLS. PS_RISE_ Total delay time is equal to PS_RISE_DELAY LCD_LSCLK periods. DELAY 0x00 Zero LCD_LSCLK periods 0x3F 63 LCD_LSCLK periods 25–24 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 21-14 Freescale Semiconductor...
Page 451 The rising edge delay of LCD_PS is programmed by PS_RISE_DELAY CLS_HI_WIDTH is equal to PWM_SCR0 • 256 + PWM_WIDTH in units of LCD_LSCLK. LCD_SPL_SPR pulse width is fixed and aligned to the first data of the line. Figure 21-13. Horizontal Timing MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-15...
Page 452: Lcdc Pwm Contrast Control Register (Lcd_Pccr)
There is a 32 × 32 bit line buffer in the LCDC that stores DMA data from system memory. The DMA control register controls the DMA burst length and when to trigger a DMA burst in terms of the number of data bytes left in the pixel buffer. MCF52277 Reference Manual, Rev. 1 21-16 Freescale Semiconductor...
Page 453: Lcdc Refresh Mode Control Register (Lcd_Rmcr)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-16. LCD Refresh Mode Control Register (LCD_RMCR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 454: Lcdc Interrupt Configuration Register (Lcd_Icr)
0 Interrupt flag is set when the end of a graphic window is reached 1 Interrupt flag is set when the beginning of a graphic window is reached Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 21-18 Freescale Semiconductor...
Page 455: Lcdc Interrupt Enable Register (Lcd_Ier)
When the interrupt is masked, the LCDC does not generate the interrupt request, but its status can be observed in the interrupt status register. Address: 0xFC0A_C03C (LCD_IER) Access: User read/write Reset Reset Figure 21-18. LCD Interrupt Endable Register (LCD_IER) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-19...
Page 456: Lcdc Interrupt Status Register (Lcd_Isr)
If any bit in this register is set and the corresponding bit in the LCD_IER register is set, an LCD interrupt is asserted to the interrupt controller. The status bit is cleared by reading the register. MCF52277 Reference Manual, Rev. 1 21-20 Freescale Semiconductor...
Page 457 Error response interrupt. Indicates whether the LCDC has issued a read data request and has received a bus error. It is cleared by reading the status register, at power on reset, or when the LCDC is disabled. 0 Interrupt has not occurred. 1 Interrupt has occurred. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-21...
Page 458: Lcdc Graphic Window Start Address Register (Lcd_Gwsar)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-21. LCD Graphic Window Size Register (LCD_GWSR) MCF52277 Reference Manual, Rev. 1 21-22...
Page 459: Lcdc Graphic Window Virtual Page Width Register (Lcd_Gwvpw)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-23. LCD Graphic Window Panning Offset Register (LCD_GWPOR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 460: Lcdc Graphic Window Position Register (Lcd_Gwpr)
Graphic window Y-position. Represents the graphic window’s vertical starting position in lines (from 0 to GW_YMAX). GWYP 21.3.23 LCDC Graphic Window Control Register (LCD_GWCR) The LCD color cursor mapping register defines the color of the cursor in passive or TFT color modes. MCF52277 Reference Manual, Rev. 1 21-24 Freescale Semiconductor...
Page 461 GWCKG 0x00 No green … 0x3F Full green 5–0 Graphic window color keying blue component. Defines the blue component of graphic window color keying. GWCKB 0x00 No blue … 0x3F Full blue MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-25...
Page 462: Lcdc Graphic Window Dma Control Register (Lcd_Gwdcr)
Unimplemented bits are read as 0. All read and write data use the least significant 12 or 18 bits. NOTE Byte or word access to the RAM corrupts its contents. MCF52277 Reference Manual, Rev. 1 21-26 Freescale Semiconductor...
Page 463 Red level (color display). Represents the red component level in the color. 7–4 Green level (color display). Represents the green component level in the color. 3–0 Blue level (color display). Represents the blue component level in the color. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-27...
Page 464 256 colors can be selected out of a palette of 256K. All 256 mapping RAM entries must be written to define the codes for the 256 available combinations. MCF52277 Reference Manual, Rev. 1 21-28...
Page 465: Functional Description
The maximum page width is specified by the virtual page width (VPW) parameter. Virtual page height (VPH) does not affect the LCDC and is limited only by memory size. By changing the SSA register, a MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 466: Graphic Window On Screen
One of the applications can be a graphical hardware cursor. NOTE The graphic window and background images must have the same bpp setting. MCF52277 Reference Manual, Rev. 1 21-30 Freescale Semiconductor...
Page 467: Panning
4 bits unused. In 18 bpp mode, 32 bits of memory are used for each pixel, leaving 14 bits unused. Refer to Figure 21-30 Figure 21-31. LCD Screen Figure 21-29. Pixel Location on Display Screen MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-31...
Page 468 Bit 26 Bit 25 Bit 24 Red1 [4] Red1 [3] Red1 [2] Red1 [1] Red1 [0] Green1 [5] Green1 [4] Green1 [3] Figure 21-30. Display Data Mapping 1 bpp Through 16 bpp Modes MCF52277 Reference Manual, Rev. 1 21-32 Freescale Semiconductor...
Page 469: Black-And-White Operation
0, 5/16, 11/16 and 1 for certain graphics. Figure 21-32 illustrates gray-scale pixel generation. The flexible mapping scheme allows the user to optimize the visual effect for a specific panel or application. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-33...
Page 470: Color Generation
For 12-, 16- and 18-bit active matrix color display, pixel data is simply moved from display memory to the LCDC output bus. Figure 21-33 Figure 21-34 illustrate passive matrix and active matrix color pixel generation. MCF52277 Reference Manual, Rev. 1 21-34 Freescale Semiconductor...
Page 471 1 1 0 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 12 bpp Data Color Inside LCDC 256 rows To panel Figure 21-33. Passive Matrix Color Pixel Generation MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-35...
Page 472: Frame Rate Modulation Control (Frc)
The LCDC can generate 16 simultaneous gray-scale levels. Table 21-33. Gray Palette Density Gray Code Density Density (Hexadecimal) (Decimal) 0.125 0.25 0.333 0.444 0.555 0.666 0.75 MCF52277 Reference Manual, Rev. 1 21-36 Freescale Semiconductor...
Page 473: Panel Interface Signals And Timing
(LCD_PCR). The data bus timing for passive panels is determined by the shift clock (LCD_LSCLK), line pulse (LCD_LP), first line marker (LCD_FLM), alternate crystal direction (LCD_ACD), and line data (LCD_D) signals. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-37...
Page 474 [0,9] [0,233] [0,237] [0,m-7] [0,m-3] LCD_D2 [0,2] [0,6] [0,10] [0,234] [0,238] [0,m-6] [0,m-2] [0,3] LCD_D3 [0,7] [0,11] [0,235] [0,239] [0,m-5] [0,m-1] Figure 21-36. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels MCF52277 Reference Manual, Rev. 1 21-38 Freescale Semiconductor...
Page 475 H_WAIT_2 defines the delay from the end of LCD_LP to the beginning of data output. NOTE LCD_PCR[PCD] ⎛ ⎞ All parameters are defined in unit of pixel clock period -------------------------------------------------- - ⎝ ⎠ sys/2 unless stated otherwise. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-39...
Page 476: Bpp Mode Color Stn Panel
1. LCD_LSCLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, LCD_LSCLK runs continuously. 2. LCD_HSYNC causes the panel to start a new line. MCF52277 Reference Manual, Rev. 1 21-40 Freescale Semiconductor...
Page 477 21-34. The unused bits are fixed at 0. Table 21-34. TFT Color Channel Assignments LCD_D[17:0] 4 bpp 8 bpp – – – – – – 12 bpp – – 16 bpp 18 bpp MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-41...
Page 478 H_WAIT_2 defines the delay from the end of LCD_HSYNC to the beginning of the LCD_OE pulse. • H_WAIT_1 defines the delay from end of LCD_OE to the beginning of the LCD_HSYNC pulse. • XMAX defines the (total) number of pixels per line. MCF52277 Reference Manual, Rev. 1 21-42 Freescale Semiconductor...
Page 479 (time = one line period) after LCD_VSYNC. The LCD_HSYNC pulse is output during the V_WAIT_2 delay. End of frame V_WIDTH Beginning of frame (lines) YMAX LCD_VSYNC LCD_HSYNC LCD_OE V_WAIT_1 V_WAIT_2 Figure 21-42. Vertical Sync Pulse Timing TFT Mode MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 21-43...
Page 480 Liquid Crystal Display Controller (LCDC) MCF52277 Reference Manual, Rev. 1 21-44 Freescale Semiconductor...
Page 481: Overview
ADC block and removing the bouncing effect. • The FIFO temporarily stores the measured data and allows the MCU to burst the measured data by using the various FIFO usage flags. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-1...
Page 482: Features
• Touchscreen mode supports auto-sampling, single-round sampling, and manual sampling modes • Touchscreen calibration and auto-zero support • Provides data-ready, FIFO full, and configurable water mark interrupts • Hardware pen detection interrupt MCF52277 Reference Manual, Rev. 1 22-2 Freescale Semiconductor...
Page 483: External Signal Description
(bits) 0xFC0A_8000 ASP Control Register (ASP_CR) 0x0008_0000 22.3.1/22-4 0xFC0A_8004 ASP Sampling Setting Register (ASP_SET) 0x7787_0000 22.3.2/22-7 0xFC0A_8008 A/D Sampling Timing Register (ASP_TIM) 0x000F_0FFF 22.3.3/22-8 0xFC0A_800C ASP Interrupt/DMA Control Register (ASP_ICR) 0x0020_0000 22.3.4/22-9 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-3...
Page 484: Asp Control Register (Asp_Cr)
If you clear this bit and set it again within a single ADC_CLK cycle, this short pulse is expanded to a longer pulse so it is captured by the ASP. 0 Stop the sequence operation. 1 Initiate the sequence operation. 30–24 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 22-4 Freescale Semiconductor...
Page 485 X and Y coordinate sample. 0 No auto-zero measurement 1 Auto-zero measurement taken before every pin input measurement Note: MIDLECNT has no affect on inserting idle phases between the auto-zero measurement and the corresponding coordinate measurement. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-5...
Page 486 APTN bits set for channels that have touchscreen functions are ignored. 0 Channel is not selected for general purpose ADC channels conversion 1 Channel is selected for general purpose ADC channels conversion MCF52277 Reference Manual, Rev. 1 22-6 Freescale Semiconductor...
Page 487: Asp Sample Setting Register (Asp_Set)
Trim value for ADC. After reset, the default value for TRIMMING is 0x87. It is strongly recommended to use the TRIMC reference value, which is TBD at this time. Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-7...
Page 488: Asp Sample Timing Register (Asp_Tim)
Idle time setting between two successive measurements. When this field is cleared, there is no idle phase MIDLECNT between two successive measurements. There is no idle phase between AZX/AZY and X/Y measurements. MCF52277 Reference Manual, Rev. 1 22-8 Freescale Semiconductor...
Page 489: Asp Interrupt/Dma Control Register (Asp_Icr)
0 Disable the pen FIFO overflow interrupt 1 Enable the pen FIFO overflow interrupt Reserved, must be cleared. Pen-up interrupt enable. PUIE 0 Disable 1 Enable Pen-down interrupt enable. PDIE 0 Disable 1 Enable MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-9...
Page 490: Asp Status Register (Asp_Sr)
Pen up flag. Indicates a pen-down event has occurred. This flag is sticky and is cleared by writing a 1 to it. Clearing this bit is processed asynchronously. 0 Pen up not detected 1 Pen up detected MCF52277 Reference Manual, Rev. 1 22-10 Freescale Semiconductor...
Page 491: Asp Sample Fifo (Asp_Sfifo)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U U U U U U U U U U U U U U U U Figure 22-7. ASP Sample FIFO Register (ASP_SFIFO) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 492: Asp Fifo Pointer Register (Asp_Fifop)
FIFO read pointer. Indicates the 4-bit FIFO read pointer. FFRP 15–6 Reserved, must be cleared. 5–0 FIFO write pointer. Indicates the 4-bit FIFO write pointer. If a writing event is in process, the write pointer may FFWP not be accurate. MCF52277 Reference Manual, Rev. 1 22-12 Freescale Semiconductor...
Page 493: Asp Clock Divider Register (Asp_Clkd)
The analog signal processor may be configured as a touchscreen or generic ADC depending on ASP_CR[TSE]. If set, the module is configured as a touchscreen controller; if cleared, the module is configured as general purpose ADC. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-13...
Page 494: Touchscreen Controller Function
ASP_CR[PENE]. Pen-up detection ise active at this time as well. No data is written The touchscreen is parked in the pen-detection state. to the FIFO MCF52277 Reference Manual, Rev. 1 22-14 Freescale Semiconductor...
Page 495 The pen detection circuit is active if ASP_SET[SW] is set. AZE has no effect when only general-purpose channels are converted. No data is written The touchscreen is parked in the pen-detection state. to the FIFO MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-15...
Page 496: General Adc Function
X/Y measurement. 22.4.2 General ADC Function When the block is configured as a general ADC (ASP_CR[TSE] = 0), the touchscreen bias network completely switches off automatically. Table 22-12 describes the block’s operation. MCF52277 Reference Manual, Rev. 1 22-16 Freescale Semiconductor...
Page 497: Initialization/Application Information
Figure 22-10 Figure 22-11 illustrate a typical operation sequence when TSE = 1, CALA = 0, MODE = 00 (AUTO, AZE, PENE, MIDLECNT, and RIDLECNT are not relevant to the operation). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-17...
Page 498 Conversion completes, result is written into FIFO, and data ready interrupt occurs. i) MCU clears ASPE to prepare for the next operation. j) MCU reads out the conversion result and the data ready interrupt is cleared automatically. MCF52277 Reference Manual, Rev. 1 22-18 Freescale Semiconductor...
Page 499: Touchscreen Mode 01—Single Round
The ASP automatically clears ASPE if PENE is set, or software must clear ASPE. i) MCU clears the pen-up interrupt. NOTE If MIDLECNT is equal to zero, remove the IDLE measurement phase. If AZE is cleared, remove the AZX and AZY measure phases. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-19...
Page 500: Touchscreen Mode 01—Auto
MCU uploads the results of one round of conversions, which clears the FIFO watermark interrupt. h) Step f and g occur repeatedly. i) FIFO watermark interrupt occurs for the last round of conversions. MCF52277 Reference Manual, Rev. 1 22-20 Freescale Semiconductor...
Page 501: Touchscreen Mode 10—Single Round
Pen-down event is detected and the pen-down interrupt occurs. c) MCU responds to the interrupt and disables the pen-down interrupt. It is recommended to clear the FIFO in this step. d) MCU sets ASPE to initiate the measurement operation. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-21...
Page 502: Touchscreen Mode 10—Auto
I DLE M easur e I DLE M easur e I DLE det ect i on M easur e I DLE SELINP PENDOWN_IRQ ASPE FIFO_WM_IRQ Figure 22-16. Mode 10 Auto, Part 1 MCF52277 Reference Manual, Rev. 1 22-22 Freescale Semiconductor...
Page 503: Touchscreen Mode 11—Single Round
Software must stop the conversion. 22.5.6 Touchscreen Mode 11—Single Round Touchscreen mode 11 single round is used for touchscreen-controlled X/Y coordinate and auxiliary channel measurement. One touch only results in one round of measurement. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-23...
Page 504: Touchscreen Mode 11—Auto
TSE = 1, CALA = 0, MODE = 11, and AUTO = 1. The following example with MIDLECNT ≠ 0, RIDLECNT ≠ 0, AZE = 1, PENE = 1. MCF52277 Reference Manual, Rev. 1 22-24 Freescale Semiconductor...
Page 505 ADC and no extra data is written into the FIFO. NOTE If MIDLECNT is equal to zero, remove the IDLE measurement phase. If AZE is cleared, remove the AZX and AZY measure phases. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-25...
Page 506: General Purpose Adc—Single Round
TSE = 0 and AUTO = 1. (CALA, MODE, AZE, TSTYP, and PENE have no effect.) The following example assumes MIDLECNT ≠ 0, RIDLECNT ≠ 0. MCF52277 Reference Manual, Rev. 1 22-26 Freescale Semiconductor...
Page 507: Touchscreen Calibration—Single Round
Figure 22-24 illustrates a typical operation sequence when TSE = 1, CALA = 1, AUTO = 0. (MODE, AZE, PENE, and RIDLECNT have no effect.) The following example assumes MIDLECNT ≠ 0. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-27...
Page 508: Touchscreen Calibration – Auto
I DLE SELREFN I DLE M easur e I DLE M easur e I DLE M easur e I DLE M easur e SELINP ASPE FIFO_WM_IRQ Figure 22-25. Touchscreen Calibration Auto, Part 1 MCF52277 Reference Manual, Rev. 1 22-28 Freescale Semiconductor...
Page 509 ASP uploads the last round of calibration data from the FIFO, which clears the FIFO watermark interrupt. NOTE If MIDLECNT is equal to zero, remove the IDLE measurement phase. If RIDLECNT is equal to zero, remove the IDLE round phase. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 22-29...
Page 510 Touchscreen Controller/Analog-to-Digital Converter MCF52277 Reference Manual, Rev. 1 22-30 Freescale Semiconductor...
Page 511: Introduction
• • • • • • • • RXIMR3 RXIMR2 Bus Interface Unit RXIMR1 RXIMR0 Clocks, Address and Data Buses, Interrupt and Test Signals Internal Bus Interface Figure 23-1. FlexCAN Block Diagram MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-1...
Page 512: The Can System
CAN bus through a transceiver. The transceiver provides the transmit drive, waveshaping, and receive/compare functions required for communicating on the CAN bus. It can also provide protection against damage to the FlexCAN caused by a defective CAN bus or defective stations. MCF52277 Reference Manual, Rev. 1 23-2 Freescale Semiconductor...
Page 513: Features
Independent of the transmission medium (an external transceiver is assumed) • Open network architecture • Multimaster bus • High immunity to EMI • Short latency time due to an arbitration scheme for high-priority messages MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-3...
Page 514: Modes Of Operation
Waits to be in idle or bus-off state, or else waits for the third bit of intermission and then checks it to be recessive • Waits for all internal activities such as arbitration, matching, move-in, and move-out to finish • Ignores its Rx input pin and drives its Tx pin as recessive MCF52277 Reference Manual, Rev. 1 23-4 Freescale Semiconductor...
Page 515: External Signal Description
Table 23-1. FlexCAN Memory Map Address Affected Affected Width Register by Hard by Soft Access Reset Value Section/Page (bits) FlexCAN Reset Reset Supervisor-only Access Registers 0xFC02_0000 FlexCAN Module Configuration 0xD890_000F 23.3.1/23-6 Register (CANMCR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-5...
Page 516: Flexcan Configuration Register (Canmcr)
Most of the fields in this register can be accessed at any time, except the MAXMB field, which should only be changed while the module is in freeze mode. MCF52277 Reference Manual, Rev. 1 23-6 Freescale Semiconductor...
Page 517 FlexCAN not ready. This bit indicates that the FlexCAN is in disable or freeze mode. This bit is read-only and it is NOTRDY cleared after the FlexCAN exits these modes. 0 FlexCAN is in normal mode, listen-only mode, or loop-back mode. h1FlexCAN is in disable or freeze mode. Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-7...
Page 518 The reset value (0xF) is equivalent to16 message buffer (MB) configuration. This field should be changed only while the module is in freeze mode. Maximum MBs in Use = MAXMB + 1 Note: MCF52277 Reference Manual, Rev. 1 23-8 Freescale Semiconductor...
Page 519: Flexcan Control Register (Canctrl)
Phase buffer segment 2. Defines the length of phase buffer segment 2 in the bit time. The valid programmable PSEG2 values are 1–7. Eqn. 23-4 Phase buffer segment 2 (PSEG2 + 1) time quanta Bus off interrupt mask. BOFFMSK 0 Bus off interrupt disabled 1 Bus off interrupt enabled MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-9...
Page 520 Lowest buffer transmitted first. Defines the ordering mechanism for message buffer transmission. LBUF 0 Message buffer with lowest ID is transmitted first 1 Lowest numbered buffer is transmitted first MCF52277 Reference Manual, Rev. 1 23-10 Freescale Semiconductor...
Page 521: Flexcan Free Running Timer Register (Timer)
Free running timer. Captured at the beginning of the identifier (ID) field of any frame on the CAN bus. This captured TIMER value is written into the TIMESTAMP entry in a message buffer after a successful reception or transmission of a message. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-11...
Page 522: Rx Mask Registers (Rxgmask, Rx14Mask, Rx15Mask)
Match for Extended Format (MB3). Match for Normal Format. (MB2). Mismatch for MB3 because of ID0. Mismatch for MB2 because of ID28. Mismatch for MB3 because of ID28, Match for MB14 (Uses RX14MASK). MCF52277 Reference Manual, Rev. 1 23-12 Freescale Semiconductor...
Page 523: Flexcan Error Counter Register (Errcnt)
If the value of TXECTR increases to be greater than 255, the ERRSTAT[FLTCONF] field is updated to reflect bus off state, and an interrupt may be issued. The value of TXECTR is then reset to zero. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-13...
Page 524: Flexcan Error And Status Register (Errstat)
Most bits in this register are read only, except for BOFFINT and ERRINT, which are interrupt flags that can be cleared by writing 1 to them. Writing 0 has no effect. Refer to Section 23.4.1, “Interrupts.” MCF52277 Reference Manual, Rev. 1 23-14 Freescale Semiconductor...
Page 525 0 Receive error counter < 96 RXWRN 1 RxErrCounter ≥ 96 Idle status. Indicates when there is activity on the CAN bus. IDLE 0 The CAN bus is not idle. 1 The CAN bus is idle. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-15...
Page 526: Interrupt Mask Register (Imask)
0 The interrupt for the corresponding buffer is disabled. 1 The interrupt for the corresponding buffer is enabled. Note: Setting or clearing an IMASK bit can assert or negate an interrupt request, if the corresponding IFLAG bit it is set. MCF52277 Reference Manual, Rev. 1 23-16 Freescale Semiconductor...
Page 527: Interrupt Flag Register (Iflag)
(0xFC02_0000). The 256-byte message buffer space is fully used by the16 message buffer structures. Each message buffer consists of a control and status field that configures the message buffer, an identifier field for frame identification, and up to 8 bytes of data. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-17...
Page 528 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Figure 23-14. Message Buffer Structure for Extended and Standard Frames MCF52277 Reference Manual, Rev. 1 23-18 Freescale Semiconductor...
Page 529 Data field. Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from 23–16, the CAN bus. For Tx frames, the CPU provides the data to be transmitted within the frame. 15–8, 7–0 DATA MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-19...
Page 530 MB automatically returns to the INACTIVE state. 1100 0100 Remote frame to be transmitted unconditionally once, and message buffer becomes an Rx message buffer with the same ID for data frames. MCF52277 Reference Manual, Rev. 1 23-20 Freescale Semiconductor...
Page 531: Rx Individual Masking Registers (Rximr0–15)
Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 23-15. FlexCAN Rx Individual Masking Registers (RXIMR0–15) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 532: Functional Overview
At the end of the successful transmission, the value of the free running timer (TIMER) is written into the message buffer’s time stamp MCF52277 Reference Manual, Rev. 1 23-22 Freescale Semiconductor...
Page 533: Arbitration Process
The write operation immediately deactivates the MB, removing it from any currently ongoing arbitration or matching process, giving time for the CPU to program the rest of the MB. After the MB is activated in MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 534: Matching Process
While the ID, DLC and data fields are retrieved from the CAN bus, they are stored temporarily in the serial message buffer (Section 23.3.16.1, “Serial Message Buffers (SMBs)”). The matching process takes place MCF52277 Reference Manual, Rev. 1 23-24 Freescale Semiconductor...
Page 535: Message Buffer Managing
To allow double buffering of messages, the FlexCAN has two shadow buffers called serial message buffers. These two buffers are used by the FlexCAN for buffering received messages and messages to be MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-25...
Page 536: Locking And Releasing Message Buffers
The lock is released when the CPU reads the free running timer (global unlock operation), or when it reads the control and status word of another MB. The MB locking is done to prevent a new frame to be written into the MB while the CPU is reading it. MCF52277 Reference Manual, Rev. 1 23-26 Freescale Semiconductor...
Page 537: Can Protocol Related Frames
The mask registers are not used in remote frame ID matching. All ID bits (except RTR) of the incoming received frame must match for the remote frame to trigger a response MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 538: Time Stamp
CAN engine. CANCTRL[CLK_SRC] Internal Bus Clock Prescaler sys/2 S clock (1 .. 256) Oscillator Clock (EXTAL) Figure 23-16. CAN Engine Clocking Scheme or EXTAL sys/2 -------------------------------------- - Eqn. 23-6 PRESDIV + 1 MCF52277 Reference Manual, Rev. 1 23-28 Freescale Semiconductor...
Page 539 CAN compliant segment settings and the related parameter values. 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 23-29...
Page 540: Initialization/Application Information
CANMCR register’s FRZ_ACK and NOT_RDY bits are set. The CANTX pin is in recessive state and the FlexCAN does not initiate any transmission or reception of CAN frames. The message buffers are not affected by reset, so they are not automatically initialized. MCF52277 Reference Manual, Rev. 1 23-30 Freescale Semiconductor...
Page 541: Interrupts
(bus off and error) act in the same manner, and are located in the ERRSTAT register. The bus off and error interrupt mask bits are located in the CANCTRL register. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 542 FlexCAN MCF52277 Reference Manual, Rev. 1 23-32 Freescale Semiconductor...
Page 543: Introduction
Channel 3 PWMOUT3 Alignment Period and Duty Counter Channel 2 Period and Duty Counter Channel 1 PWMOUT1 Period and Duty Counter Channel 0 Period and Duty Counter Figure 24-1. PWM Block Diagram MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-1...
Page 544: Memory Map/Register Definition
PWM Scale B Register (PWMSCLB) 0x00 24.2.8/24-8 0xFC09_002C + n PWM Channel n Counter Register (PWMCNTn) 0x00 24.2.9/24-9 n = 0–7 0xFC09_0034 + n PWM Channel n Period Register (PWMPERn) 0xFF 24.2.10/24-10 n = 0–7 MCF52277 Reference Manual, Rev. 1 24-2 Freescale Semiconductor...
Page 545: Pwm Enable Register (Pwme)
PWM Channel 3 Output Enable. If enabled, the PWM signal becomes available at PWMOUT3 when its PWME3 corresponding clock source begins its next cycle. 0 PWM output disabled 1 PWM output enabled Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-3...
Page 546: Pwm Polarity Register (Pwmpol)
PWMCLK[PCLKn] control bits. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Address: 0xFC09_0022 (PWMCLK) Access: User Read/Write PCLK7 PCLK5 PCLK3 PCLK1 Reset: Figure 24-4. PWM Clock Select Register (PWMCLK) MCF52277 Reference Manual, Rev. 1 24-4 Freescale Semiconductor...
Page 547: Pwm Prescale Clock Select Register (Pwmprclk)
Clock B prescaler select. These three bits control the rate of Clock B, which can be used for PWM channels 3 and 7. PCKB PCKB Clock B Rate Internal bus clock ÷ 2 Internal bus clock ÷ 2 Internal bus clock ÷ 2 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-5...
Page 548: Pwm Center Align Enable Register (Pwmcae)
The PWMCTL register provides various control of the PWM module. Change the CONn(n+1) bits only when both corresponding channels are disabled. See Section 24.3.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation function. MCF52277 Reference Manual, Rev. 1 24-6 Freescale Semiconductor...
Page 549: Pwm Scale A Register (Pwmscla)
Clock A Clock SA ---------------------------------------- - Eqn. 24-1 × PWMSCLA Any value written to this register causes the scale counter to load the new scale value (PWMSCLA). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-7...
Page 550: Pwm Scale B Register (Pwmsclb)
Any value written to this register causes the scale counter to load the new scale value (PWMSCLB). Address: 0xFC09_0029 (PWMSCLB) Access: User Read/Write SCALEB Reset: Figure 24-9. PWM Scale B Register (PWMSCLB) MCF52277 Reference Manual, Rev. 1 24-8 Freescale Semiconductor...
Page 551: Pwm Channel Counter Registers (Pwmcntn)
Section 24.3.2.4, “PWM Timer Counters.” Address: 0xFC09_002C (PWMCNT0) Access: User Read/Write 0xFC09_002D (PWMCNT1) 0xFC09_002E (PWMCNT2) 0xFC09_002F (PWMCNT3) 0xFC09_0030 (PWMCNT4) 0xFC09_0031 (PWMCNT5) 0xFC09_0032 (PWMCNT6) 0xFC09_0033 (PWMCNT7) COUNT Reset: Figure 24-10. PWM Counter Registers (PWMCNTn) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-9...
Page 552: Pwm Channel Period Registers (Pwmpern)
(high time as a percentage of period) for a particular channel: PWMDTYn ⎛ ⎞ × Duty Cycle 1 PWMPOL PPOLn – – 100% ----------------------------- - Eqn. 24-4 ⎝ ⎠ PWMPERn MCF52277 Reference Manual, Rev. 1 24-10 Freescale Semiconductor...
Page 553: Pwm Shutdown Register (Pwmsdn)
The PWM shutdown register provides emergency shutdown functionality of the PWM module. The PWMSDN[7:1] bits are ignored if PWMSDN[SDNEN] is cleared. : 0xFC09_0044 (PWMSDN) Access: Read/Write PWM7IN PWM7IL SDNEN RESTART Reset: Figure 24-13. PWM Shutdown Register (PWMSDN) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-11...
Page 554: Functional Description
PWM channel has the capability of selecting one of two clocks, the prescaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 24-14 shows the four different clocks and how the scaled clocks are created. MCF52277 Reference Manual, Rev. 1 24-12 Freescale Semiconductor...
Page 555 Clock A and B are scaled values of the input clock. The value is software selectable for clock A and B and has options of 1, 1/2,..., or 1/128 times the internal bus clock. The value selected for clock A and B is determined by the PWMPRCLK[PCKAn] and PWMPRCLK[PCKBn] bits. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-13...
Page 556: Pwm Channel Timers
The starting polarity of the output is also selectable on a per channel basis. Figure 24-15 shows a block diagram for a PWM timer. MCF52277 Reference Manual, Rev. 1 24-14 Freescale Semiconductor...
Page 557 A change in duty or period can be forced into effect immediately by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 558 When PWMCNTn register written to any When PWM channel is enabled When PWM channel is disabled value (PWMEn = 1). Counts from last value (PWMEn = 0) in PWMCNTn. Effective period ends MCF52277 Reference Manual, Rev. 1 24-16 Freescale Semiconductor...
Page 559 PWMn frequency = 83.3 MHz ÷ 4 = 20.8 MHz PWMn period = 48 ns ⎛ ⎞ × PWMn Duty Cycle – 100% -- - ⎝ ⎠ The output waveform generated is below: MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-17...
Page 560 Clock (A, B, SA, or SB) PWMn frequency --------------------------------------------------------- - Eqn. 24-9 × WMPERn The PWMn duty cycle (high time as a percentage of period) is expressed as: MCF52277 Reference Manual, Rev. 1 24-18 Freescale Semiconductor...
Page 561 In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to the low or high order byte of the counter resets the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-19...
Page 562 PPOL1 PCLK1 CAE1 PWMOUT1 24.3.2.8 PWM Boundary Cases The following table summarizes the boundary conditions for the PWM regardless of the output mode (left- or center-aligned) and 8-bit (normal) or 16-bit (concatenation): MCF52277 Reference Manual, Rev. 1 24-20 Freescale Semiconductor...
Page 563 • Changed references from “core clock” to — (EDS) “internal bus clock” • Added customer version of Figure 24-14 — 11 May 2004 E Southers • Added customer version of Figure 24-15 — (EDS) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-21...
Page 564 Kirin2e Rev. 2 — 7 Jul 2006 E Southers Minime/DF/ST Rev. 1 (EDS) — 25 Aug 2006 • Added Kirin2e conditional tag and — Tsurikov assigned it to entries tagged for Kirin. (MST) MCF52277 Reference Manual, Rev. 1 24-22 Freescale Semiconductor...
Page 565 Kirin0u Rev 0 Draft B (MST) 12 Mar 2007 M Tsurikov Preparation for Kirin Rev. 3 (MST) 19 Mar 07 J Davis Light edit for corrections in grammar, style, (JMD) punctuation, and formatting. Kirin Rev. 3 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-23...
Page 566 11 Sep 2007 J Davis Release of Kirin2e, Rev. 5 (JMD) 1.28 12 Sep 2007 M Tsurikov Continue preparation for Kirin0u Rev. 2 (MST) 1.29 14 Sep 2007 M Tsurikov Kirin0u Rev. 2 (MST) MCF52277 Reference Manual, Rev. 1 24-24 Freescale Semiconductor...
Page 567 12 Feb 2008 D Saldana Kirin3 Rev. 0 Draft A (MDS) 1.34 22 Feb 2008 E Southers Prep for DragonFire0 Rev 1 (EDS) 1.35 02/29/08 J Davis Public Release of DragonFire0 Rev 1 (JMD) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 24-25...
Page 568 Pulse-Width Modulation (PWM) Module MCF52277 Reference Manual, Rev. 1 24-26 Freescale Semiconductor...
Page 569: Introduction
This device contains SSI bits to control the clock rate and the SSI DMA request sources within the chip configuration module (CCM). See Chapter 9, “Chip Configuration Module (CCM),” for detailed information on these bit fields. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-1...
Page 570: Overview
Such serial devices are: • Standard codecs • Digital signal processors (DSPs) • Microprocessors • Peripherals ® • Audio codecs that implement the inter-IC sound bus (I S) and the Intel AC97 standards MCF52277 Reference Manual, Rev. 1 25-2 Freescale Semiconductor...
Page 571: Features
• Gated clock mode These modes can be programmed via the SSI control registers. Table 25-1 lists these operating modes and some of the typical applications in which they can be used: MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-3...
Page 572 In slave modes, the SSI’s programmed frame length setting (DC bits) can be lesser than or equal to the frame length setting of the master (external codec). Section 25.4.1, “Detailed Operating Mode Descriptions,” for more details on the above modes. MCF52277 Reference Manual, Rev. 1 25-4 Freescale Semiconductor...
Page 573: External Signal Description
MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 574 Continuous SSI_BCLK SSI_FS Early SSI_FS Gated SSI_BCLK SSI_TXD 8-bit Data SSI_RXD Bit Length Frame Sync Word Length Frame Sync Figure 25-3. Serial Clock and Frame Sync Timing MCF52277 Reference Manual, Rev. 1 25-6 Freescale Semiconductor...
Page 575: Memory Map/Register Definition
0xFC0B_C040 SSI AC97 Command Data Register (SSI_ACDAT) 0x0000_0000 25.3.16/25-29 0xFC0B_C044 SSI AC97 Tag Register (SSI_ATAG) 0x0000_0000 25.3.17/25-29 0xFC0B_C048 SSI Transmit Time Slot Mask Register (SSI_TMASK) 0x0000_0000 25.3.18/25-29 0xFC0B_C04C SSI Receive Time Slot Mask Register (SSI_RMASK) 0x0000_0000 25.3.19/25-30 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-7...
Page 576: Ssi Transmit Data Registers 0 & 1 (Ssi_Tx0/1)
The data to be transmitted occupies the most significant portion of the shift register if SSI_TCR[TXBIT0] is cleared. Otherwise, it occupies the least significant portion. The unused portion of the register is ignored. MCF52277 Reference Manual, Rev. 1 25-8 Freescale Semiconductor...
Page 577 Figure 25-5. Transmit Data Path (TXBIT0=0, TSHFD=0) (msb Alignment) SSI_TX 12 bits 16 bits 20 bits 24 bits TXSR 16 bits 20 bits 24 bits 12 bits SSI_TXD Figure 25-6. Transmit Data Path (TXBIT0=0, TSHFD=1) (msb Alignment) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-9...
Page 578: Ssi Receive Data Registers 0 & 1 (Ssi_Rx0/1)
SSI receive data. SSI_RX0/1 are implemented as the first word of their respective Rx FIFOs. These bits receive data SSI_RX from RXSR depending on the mode of operation. If both FIFOs are in use, data is transferred to each data register alternately. SSI_RX1 is only used in two-channel mode. MCF52277 Reference Manual, Rev. 1 25-10 Freescale Semiconductor...
Page 579: Ssi Receive Fifo 0 & 1 Registers
WL, which can be extended for the other values. SSI_RX 12 bits 16 bits 20 bits 24 bits RXSR 16 bits 20 bits 24 bits 12 bits SSI_RXD Figure 25-10. Receive Data Path (RXBIT0=0, RSHFD=0) (msb Alignment) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-11...
Page 580: Ssi Control Register (Ssi_Cr)
Figure 25-13. Receive Data Path (RXBIT0=1, RSHFD=1) (lsb Alignment) 25.3.7 SSI Control Register (SSI_CR) The SSI control register sets up the SSI modules. SSI operating modes are selected in this register (except AC97 mode, which is selected in SSI_ACR register). MCF52277 Reference Manual, Rev. 1 25-12 Freescale Semiconductor...
Page 581 Synchronous mode enable. In synchronous mode, transmit and receive sections of SSI share a common clock port (SSI_BCLK) and frame sync port (SSI_FS). 0 Reserved. 1 Synchronous mode selected. Network mode enable. 0 Network mode not selected 1 Network mode selected MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-13...
Page 582: Ssi Interrupt Status Register (Ssi_Isr)
All flags in the SSI_ISR are updated after the first bit of the next SSI word has completed transmission or reception. Some status bits (ROE0/1 and TUE0/1) are cleared by reading the SSI_ISR followed by a read or write to the SSI_RX0/1 or SSI_TX0/1 registers. MCF52277 Reference Manual, Rev. 1 25-14 Freescale Semiconductor...
Page 583 It causes the receive tag interrupt if the SSI_IER[RXT] bit is set. This bit is cleared upon reading the SSI_ATAG register. 0 No change in SSI_ATAG register 1 SSI_ATAG register updated with different value MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-15...
Page 584 • At least one empty slot in Tx • Tx FIFO1 is full FIFO1 • SSI reset • POR reset Disabled • SSI_TX1 data transferred to • SSI_TX1 is written TXSR • SSI reset • POR reset MCF52277 Reference Manual, Rev. 1 25-16 Freescale Semiconductor...
Page 585 Enabled • TXSR is empty • Reading SSI_ISR when TUE1 is • SSI_ISR[TDE1] set Disabled • Transmit time slot occurs • SSI reset • POR reset MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-17...
Page 586 Normal • RFS is always set • SSI reset • POR reset Network • First time slot received • Starts receiving next time slot • SSI reset • POR reset MCF52277 Reference Manual, Rev. 1 25-18 Freescale Semiconductor...
Page 587 Receive FIFO full 0. Similar to description of RFF1, but pertains to Rx FIFO 0 and is not necessary to be in RFF0 two-channel mode for this bit to be set. 0 Space available in receive FIFO 0 1 Receive FIFO 0 is full MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-19...
Page 588: Ssi Interrupt Enable Register (Ssi_Ier)
Address: 0xFC0B_C018 (SSI_IER) Access: User read/write RDMAE RIE TDMAE CMDU Reset RDR1 RDR0 TDE1 TDE0 ROE1 ROE0 TUE1 TUE0 TFS RFF1 RFF0 TFE1 TFE0 Reset Figure 25-16. SSI Interrupt Enable Register (SSI_IER) MCF52277 Reference Manual, Rev. 1 25-20 Freescale Semiconductor...
Page 589: Ssi Transmit Configuration Register (Ssi_Tcr)
SSI_TCR bits. However, an SSI reset does not affect the SSI_TCR bits. Address: 0xFC0B_C01C (SSI_TCR) Access: User read/write Reset TFEN1 TFEN0 TFDIR TXDIR TSHFD TSCKP TFSI TFSL TEFS BIT0 Reset Figure 25-17. SSI Transmit Configuration Register (SSI_TCR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-21...
Page 590 (TFSL = 0). The frame sync can also be initiated upon receiving the first bit of data. 0 Transmit frame sync initiated as first bit of data transmits 1 Transmit frame sync is initiated one bit before the data transmits MCF52277 Reference Manual, Rev. 1 25-22 Freescale Semiconductor...
Page 591: Ssi Receive Configuration Register (Ssi_Rcr)
0 Gated clock mode disabled 1 Gated clock mode enabled Receive shift direction. Controls whether the msb or lsb is received first in a sample. RSHFD 0 Data received msb first 1 Data received lsb first MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-23...
Page 592: Ssi Clock Control Register (Ssi_Ccr)
Prescaler range. Controls a fixed divide-by-eight prescaler in series with the variable prescaler. It extends the range of the prescaler for those cases where a slower bit clock is required. 0 Prescaler bypassed 1 Prescaler enabled to divide the clock by 8 MCF52277 Reference Manual, Rev. 1 25-24 Freescale Semiconductor...
Page 593: Ssi Fifo Control/Status Register (Ssi_Fcsr)
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 Figure 25-20. SSI FIFO Control/Status Register (SSI_FCSR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 594 Transmit FIFO empty watermark 0. Controls the threshold for when the SSI_ISR[TFE0] flag is set. TFE0 is set when TFWM0 the data level in Tx FIFO 0 falls below the selected threshold. See TFWM1 for bit settings. MCF52277 Reference Manual, Rev. 1 25-26 Freescale Semiconductor...
Page 595: Ssi Ac97 Control Register (Ssi_Acr)
The SSI automatically clears this bit after completing transmission of a frame. 0 Next frame does not have a write command 1 Next frame does have a write command Note: Do not set WR and RD at the same time. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-27...
Page 596: Ssi Ac97 Command Address Register (Ssi_Acadd)
SSI_ACR[WR and RD] bits). A direct write from the core or the information received in the incoming command address slot can update these bits. If contents of these bits change due to an update, the SSI_ISR[CMDAU] bit is set. MCF52277 Reference Manual, Rev. 1 25-28...
Page 597: Ssi Ac97 Command Data Register (Ssi_Acdat)
Note: Bits 1–0 convey the codec-ID. Because only primary codecs are supported, these bits must be cleared. 25.3.18 SSI Transmit Time Slot Mask Register (SSI_TMASK) This register controls the time slots that the SSI transmits data in network mode. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-29...
Page 598: Ssi Receive Time Slot Mask Register (Ssi_Rmask)
1 Time slot masked (no data received in this time slot) 25.4 Functional Description 25.4.1 Detailed Operating Mode Descriptions The following sections describe in detail the main operating modes of the SSI module: normal, network, gated clock, I S, and AC97. MCF52277 Reference Manual, Rev. 1 25-30 Freescale Semiconductor...
Page 599: Normal Mode
1. SSI enabled (SSI_CR[SSI_EN] = 1) 2. Enable receive FIFO (optional) 3. Receiver enabled (RE = 1) 4. Frame sync active (for continuous clock case) 5. Bit clock begins (for gated clock case) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-31...
Page 600 SSI_RXD input, and at the end of the time slot, this data transfers to the Rx data register. In internal gated clock mode, the Tx data line and clock output port are MCF52277 Reference Manual, Rev. 1 25-32...
Page 601 The period of the serial bit clock (PSR, PM bits for internal clock, or the frequency of the external clock on the SSI_BCLK pin) • The number of bits per sample (WL bits) • The number of time slots per frame (DC bits) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-33...
Page 602 TE bit enables transmission from the next frame. During that time the SSI_TXD port is disabled. The TE bit should be cleared after the TDE bit is set to ensure that all pending data is transmitted. MCF52277 Reference Manual, Rev. 1 25-34...
Page 603 8-bit word with continuous clock, FIFO disabled, three words per frame sync in network mode. NOTE The transmitter repeats the value 0x5E because of an underrun condition. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-35...
Page 604 (ROE) flag is set on reception of the next data (0x5E). The ROE flag is cleared by reading the SSI status register followed by reading the Rx data register. MCF52277 Reference Manual, Rev. 1 25-36...
Page 605 SSI_RXD signals. For this reason, no frame sync is needed in this mode. After transmission of data completes, the clock is pulled to the inactive state. Gated clocks are allowed for the transmit and receive MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 606 SSI_RXD TSCKP=1, RSCKP=1 Figure 25-32. Internal Gated Mode Timing - Falling Edge Clocking/Rising Edge Latching SSI_BCLK SSI_TXD SSI_RXD TSCKP=0, RSCKP=0 Figure 25-33. External Gated Mode Timing - Rising Edge Clocking/Falling Edge Latching MCF52277 Reference Manual, Rev. 1 25-38 Freescale Semiconductor...
Page 607 S slave mode Normal mode In normal (non-I S) mode operation, no register bits are forced to any particular state internally, and the user can program the SSI to work in any operating condition. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-39...
Page 608 S Slave Mode In I S slave mode (SSI_CR[I2S] = 10), the following additional settings are recommended: • External generated bit clock (SSI_TCR[TXDIR] = 0) • External generated frame sync (SSI_TCR[TFDIR] = 0) MCF52277 Reference Manual, Rev. 1 25-40 Freescale Semiconductor...
Page 609: Ac97 Mode
Tx frame sync length is one-word-long-frame (SSI_TCR[TFSL] = 0) • Rx frame sync length is one-word-long-frame (SSI_RCR[RFSL] = 0) • Tx frame sync initiated one bit before data is transmitted (SSI_TCR[TEFS] = 1) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-41...
Page 610 SSI should be idle, after operating for one frame. The following shows the slot assignments in a valid transmit frame: • Slot 0: The tag value (written by the user program) MCF52277 Reference Manual, Rev. 1 25-42 Freescale Semiconductor...
Page 611: Ssi Clocking
SSI_CR[MCE] bit. This serial master clock is an oversampling clock of the frame sync clock (SSI_FS). In this mode, the word length (WL), prescaler range MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 612 When internally generated, receive and transmit frame sync generate from the word clock and are defined by the frame rate divider (DC) bits and the word length (WL) bits of the SSI_CCR. MCF52277 Reference Manual, Rev. 1 25-44 Freescale Semiconductor...
Page 613 Table 25-22. SSI Bit Clock and Frame Rate as a Function of PSR, PM, and DIV2 SSI_CLKIN SSI_CCR Bit Clk (kHz) Frame rate freq (MHz) SSI_BCLK (kHz) (SSI_MCLK) DIV2 PSR 12.288 12.288 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-45...
Page 614: External Frame And Clock Operation
SSI_TX0/1 and SSI_RX0/1 based on the data format and the number of bits per word. Independent data formats are supported for the transmitter and receiver (i.e. the transmitter and receiver can use different data formats). MCF52277 Reference Manual, Rev. 1 25-46 Freescale Semiconductor...
Page 615 In sign-extension, all bits above the most significant bit are equal to the most significant bit. This format is useful when data is stored in a fixed-point integer format (which implies fractional values). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-47...
Page 616: Receive Interrupt Enable Bit Description
Tx FIFO 1). If not enabled, then one value can be written to the SSI_TX0 register (one per channel in two-channel mode using SSI_TX1). When the TIE bit is cleared, all transmit interrupts are disabled. However, the TDE0/1 bits always indicate the corresponding SSI_TX register MCF52277 Reference Manual, Rev. 1 25-48 Freescale Semiconductor...
Page 617: Initialization/Application Information
To ensure proper operation of the SSI, use the power-on or SSI reset before changing any of the control bits listed in Table 25-27. NOTE These control bits should not be changed when SSI module is enabled. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 25-49...
Page 618 [8]=RFEN1 & TFEN1 [7]=RFEN0 & TFEN0 [6]=TFDIR SSI_RCR [5]=RXDIR & TXDIR SSI_TCR [4]=RSHFD & TSHFD [3]=RSCKP & TSCKP [2]=RFSI & TFSI [1]=RFSL & TFSL [0]=REFS & TEFS SSI_CCR [16:13]=WL [1]=FV SSI_ACR [10:5]=FRDIV MCF52277 Reference Manual, Rev. 1 25-50 Freescale Semiconductor...
Page 619: Introduction
Figure 26-1. Real Time Clock Block Diagram 26.1.1 Overview This section discusses how to operate and program the real-time clock (RTC) module that maintains a time-of-day clock, provides stopwatch, alarm, and interrupt functions, and supports the following features. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 26-1...
Page 620: Features
Sampling frequencies are dependent upon the RTC oscillator frequency and the value in RTC_GOC[31:9]. • Minute Stopwatch MCF52277 Reference Manual, Rev. 1 26-2 Freescale Semiconductor...
Page 621: External Signal Description
This register programs the hours and minutes for the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. This register cannot be reset because the real-time clock is always enabled at reset. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 26-3...
Page 622: Rtc Seconds Counter Register (Rtc_Seconds)
SECONDS 26.3.3 RTC Hours and Minutes Alarm Register (RTC_ALRM_HM) The RTC_ALRM_HM register configures the hours and minutes setting for the alarm. The alarm settings can be read or written at any time. MCF52277 Reference Manual, Rev. 1 26-4 Freescale Semiconductor...
Page 623: Rtc Seconds Alarm Register (Rtc_Alrm_Sec)
Seconds setting of the alarm. The value written to this field must be the alarm time desired minus one second. Set SECONDS to any value between 0 and 59 (0x3B). 26.3.5 RTC Control Register (RTC_CR) The RTC_CR register enables the real-time clock module and specify the reference frequency information for the prescaler. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 26-5...
Page 624: Rtc Interrupt Status Register (Rtc_Isr)
Interrupts may occur while the system clock is idle or in sleep mode. Address: 0xFC03_C014 (RTC_ISR) Access: User read/write Reset R SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0 2HZ W w1c Reset Figure 26-7. RTC Interrupt Status Register (RTC_ISR) MCF52277 Reference Manual, Rev. 1 26-6 Freescale Semiconductor...
Page 625: Rtc Interrupt Enable Register (Rtc_Ier)
1 The stopwatch timed out 26.3.7 RTC Interrupt Enable Register (RTC_IER) The RTC_IER register enables/disables the various real-time clock interrupts. Masking an interrupt bit has no effect on its corresponding status bit. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 26-7...
Page 626 1 Stopwatch interrupt enabled. The stopwatch counts down and remains at decimal -1 until it is reprogrammed. If this bit is enabled with RTC_STPWCF equaling 0x3F, an interrupt is requested on the next minute tick. MCF52277 Reference Manual, Rev. 1 26-8...
Page 627: Rtc Stopwatch Minutes Register (Rtc_Stpwch)
Current day count. Set to any value between 0 and 65,535 (0xFFFF). DAYS 26.3.10 RTC Day Alarm Register (RTC_ALRM_DAY) The RTC_ALRM_DAY register configures the day for the alarm. The alarm settings can be read or written at any time. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 26-9...
Page 628: Rtc General Oscillator Clock Upper Register (Rtc_Gocu)
RTC oscillator clock to create a 1 Hz and sample frequencies. This register can be read or written at any time. A non-zero value must be programmed into RTC_GOC for the 1 Hz internal clock to function. MCF52277 Reference Manual, Rev. 1 26-10...
Page 629: Functional Description
59 to 00, the minute counter increments and the MIN interrupt flag is set. The same is true for the minute counter with the HR signal and the hour counter with the DAY signal. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 630: Alarm
16.13 Hz 16.00 Hz 16.00 Hz 16.13 SAM1 8.06 Hz 8.00 Hz 8.00 Hz 8.06 Hz SAM0 4.03 Hz 4.00 Hz 4.00 Hz 4.03 Hz 2.02 Hz 2.00 Hz 2.00 Hz 2.02 Hz MCF52277 Reference Manual, Rev. 1 26-12 Freescale Semiconductor...
Page 631: Minute Stopwatch
Figure 26-14. Flow Chart of RTC Operation 26.5.2 Programming the Alarm or Time-of-Day Registers Use the following procedure illustrated in Figure 26-15 when changing the alarm or time-of-day (day, hour, minute, and second) registers. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 26-13...
Page 632 Program the alarm or time-of-day registers Clear any incidental alarm interrupt during programming (write 1 to RTC_ISR[ALM]) Enable the alarm interrupt (set RTC_IER[ALM] Figure 26-15. Flow Chart of Alarm and Time-of-Day Programming MCF52277 Reference Manual, Rev. 1 26-14 Freescale Semiconductor...
Page 633: Introduction
Low-power modes are described in the power management module, Chapter 8, “Power Management.” Table 27-1 shows the PIT module operation in low-power modes and how it can exit from each mode. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 27-1...
Page 634: Memory Map/Register Definition
Register Access Reset Value Section/Page PIT 0 (bits) PIT 1 Supervisor Access Only Registers 0xFC08_0000 PIT Control and Status Register (PCSRn) 0x0000 27.2.1/27-3 0xFC08_4000 0xFC08_0002 PIT Modulus Register (PMRn) 0xFFFF 27.2.2/27-4 0xFC08_4002 MCF52277 Reference Manual, Rev. 1 27-2 Freescale Semiconductor...
Page 635: Pit Control And Status Register (Pcsrn)
Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN bit stops the prescaler counter. Internal Bus Clock Decimal Divisor Equivalent 0000 0001 0010 1101 8192 1110 16384 1111 32768 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 27-3...
Page 636: Pit Modulus Register (Pmrn)
PIT counter. The prescaler counter is reset (0xFFFF) anytime a new value is loaded into the PIT counter and also during reset. Reading the PMRn returns the value written in the modulus latch. Reset initializes PMRn to 0xFFFF. MCF52277 Reference Manual, Rev. 1 27-4 Freescale Semiconductor...
Page 637: Pit Count Register (Pcntrn)
When PIT counter reaches a count of 0x0000, PIF flag is set in PCSRn. The value in the modulus register loads into the counter, and the counter begins decrementing toward 0x0000. If the PCSRn[PIE] bit is set, the PIF flag issues an interrupt request to the CPU. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 27-5...
Page 638: Free-Running Timer Operation
PCSRn[PRE] bits. The PMRn[PM] bits select the timeout period. × Timeout period PRE[3:0] (PM[15:0] × Eqn. 27-1 sys 2 ⁄ 27.3.4 Interrupt Operation Table 27-6 shows the interrupt request generated by the PIT. MCF52277 Reference Manual, Rev. 1 27-6 Freescale Semiconductor...
Page 639 The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 640 Programmable Interrupt Timers (PIT0–PIT1) MCF52277 Reference Manual, Rev. 1 27-8 Freescale Semiconductor...
Page 641: Introduction
DMA transfer on a particular event. NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 14, “General Purpose I/O Module”) prior to configuring the DMA Timers. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 28-1...
Page 642: Features
• Ability to stop the timer from counting when the ColdFire core is halted 28.2 Memory Map/Register Definition The timer module registers, shown in Table 28-1, can be modified at any time. MCF52277 Reference Manual, Rev. 1 28-2 Freescale Semiconductor...
Page 643: Dma Timer Mode Registers (Dtmrn)
DMA Timer Mode Registers (DTMRn) DTMRs, shown in Figure 28-2, program the prescaler and various timer modes. Address: 0xFC07_0000 (DTMR0) Access: User read/write 0xFC07_4000 (DTMR1) 0xFC07_8000 (DTMR2) 0xFC07_C000 (DTMR3) ORRI FRR Reset Figure 28-2. DTMRn Registers MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 28-3...
Page 644: Dma Timer Extended Mode Registers (Dtxmrn)
The DTXMRn register programs DMA request and increment modes for the timers. Address: 0xFC07_0002 (DTXMR0) Access: User read/write 0xFC07_4002 (DTXMR1) 0xFC07_8002 (DTXMR2) 0xFC07_C002 (DTXMR3) DMAEN HALTED MODE16 Reset: Figure 28-3. DTXMRn Registers MCF52277 Reference Manual, Rev. 1 28-4 Freescale Semiconductor...
Page 645: Dma Timer Event Registers (Dtern)
If configured to generate a DMA request, processing of the DMA data transfer automatically clears the REF and CAP flags via the internal DMA ACK signal. Address: 0xFC07_0003 (DTER0) Access: User read/write 0xFC07_4003 (DTER1) 0xFC07_8003 (DTER2) 0xFC07_C003 (DTER3) Reset: Figure 28-4. DTERn Registers MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 28-5...
Page 646: Dma Timer Reference Registers (Dtrrn)
(DTCNn) as part of the output-compare function. The reference value is not matched until DTCNn equals DTRRn, and the prescaler indicates that DTCNn should be incremented again. Therefore, the reference register is matched after DTRRn + 1 time intervals. MCF52277 Reference Manual, Rev. 1 28-6 Freescale Semiconductor...
Page 647: Dma Timer Capture Registers (Dtcrn)
The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Any write to DTCNn clears it. The timer counter increments on the clock source rising edge (internal bus clock divided by 1, internal bus clock divided by 16, or DTnIN). MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 28-7...
Page 648: Functional Description
When a timer reaches the reference value selected by DTRR, it can send an output signal on DTnOUT. DTnOUT can be an active-low pulse or a toggle of the current output, as selected by the DTMRn[OM] bit. MCF52277 Reference Manual, Rev. 1 28-8...
Page 649: Initialization/Application Information
*[OM] = 0 output=active-low pulse *[ORRI] = 0, disable ref. match output *[FRR] = 1, restart mode enabled *[CLK] = 10, internal bus clock/16 *[RST] = 0, timer0 disabled move.w #0xFF0C,D0 move.w D0,TMR0 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 28-9...
Page 650: Calculating Time-Out Values
For example, if a 83.33-MHz timer clock is divided by 16, DTMRn[PS] equals 0x7F, and the timer is referenced at 0x13DC3 (81347 decimal), the time-out period is: × × × Timeout period 81347 2.00 s ------------------------ - Eqn. 28-2 × 83.3 MCF52277 Reference Manual, Rev. 1 28-10 Freescale Semiconductor...
Page 651: Introduction
MCU and an external peripheral device. The DSPI supports up to 32 queued SPI transfers (16 receive and 16 transmit) in the DSPI resident FIFOs eliminating CPU intervention between transfers. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-1...
Page 652: Features
– FIFO overflow (attempt to transmit with an empty TX FIFO or serial frame received while RX FIFO is full) (RFOF) – FIFO overrun (logical OR of RX overflow and TX underflow interrupts) MCF52277 Reference Manual, Rev. 1 29-2 Freescale Semiconductor...
Page 653: Modes Of Operation
DSPI stops while in module disable mode. The DSPI enters the module disable mode when the DSPI_MCR[MDIS] bit is set. See Section 29.4.7, “Power Saving Features,” for more details on the module disable mode. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-3...
Page 654: External Signal Description
The DSPI_PCS[2,4] signals are peripheral chip select output signals in master mode. In slave mode, these signals are not used. 29.2.4 Serial Input (DSPI_SIN) DSPI_SIN is a serial data input signal. 29.2.5 Serial Output (DSPI_SOUT) DSPI_SOUT is a serial data output signal. MCF52277 Reference Manual, Rev. 1 29-4 Freescale Semiconductor...
Page 655: Serial Clock (Dspi_Sck)
MDIS bits can be changed at any time, but only take effect on the next frame boundary. Only the HALT and MDIS bits in the DSPI_MCR may be changed while the DSPI is running. NOTE The DSPI_MCR[MDIS] bit is set at reset. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-5...
Page 656 Section 29.4.4.4, “Modified SPI MTFE Transfer Format (MTFE = 1, CPHA = 1),” for more information. 0 Modified SPI transfer format disabled 1 Modified SPI transfer format enabled Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 29-6 Freescale Semiconductor...
Page 657 Reserved, must be cleared. Halt. Starts and stops DSPI transfers. See Section 29.4.1, “Start and Stop of DSPI Transfers,” for details on the HALT operation of this bit. 0 Start transfers 1 Stop transfers MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-7...
Page 658: Dspi Transfer Count Register (Dspi_Tcr)
In slave mode, a subset of the bit fields in the DSPI_CTAR0 registers sets the slave transfer attributes. See the individual bit descriptions for details on which bits are used in slave modes. MCF52277 Reference Manual, Rev. 1 29-8 Freescale Semiconductor...
Page 659 0 The baud rate is computed normally with a 50/50 duty cycle 1 Baud rate is doubled with the duty cycle depending on the baud rate prescaler CPHA SCK Duty Cycle 50/50 50/50 33/66 40/60 43/57 50/50 66/33 60/40 57/43 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-9...
Page 660 00 1 clock DSPI_PCS to DSPI_SCK delay prescaler 01 3 clock DSPI_PCS to DSPI_SCK delay prescaler 10 5 clock DSPI_PCS to DSPI_SCK delay prescaler 11 7 clock DSPI_PCS to DSPI_SCK delay prescaler MCF52277 Reference Manual, Rev. 1 29-10 Freescale Semiconductor...
Page 661 1011 4096 0100 1100 8192 0101 1101 16384 0110 1110 32768 0111 1111 65536 Note: See Section 29.4.3.2, “PCS to SCK Delay (tCSC),” for details on calculating the PCS to SCK delay. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-11...
Page 662 0011 1011 4096 0100 1100 8192 0101 1101 16384 0110 1110 32768 0111 1111 65536 Note: See Section 29.4.3.4, “Delay after Transfer (tDT),” for more details on calculating the delay after transfer. MCF52277 Reference Manual, Rev. 1 29-12 Freescale Semiconductor...
Page 663: Dspi Status Register (Dspi_Sr)
DSPI_SR by writing a 1 to it. Writing a 0 to a flag bit has no effect. Address 0xFC05_C02C (DSPI_SR) Access: User Read/Write R TCF TXRXS EOQF TFUF TFFF RFOF RFDF W w1c Reset TXCTR TXNXTPTR RXCTR POPNXTPTR Reset Figure 29-5. DSPI_SR Register MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-13...
Page 664 0 RX FIFO is empty 1 RX FIFO is not empty Note: In the interrupt service routine, RFDF must be cleared only after the DSPI_POPR register is read. Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 29-14 Freescale Semiconductor...
Page 665: Dspi Dma/Interrupt Request Select And Enable Register (Dspi_Rser)
Field Description Transmission complete request enable. Enables DSPI_SR[TCF] flag to generate an interrupt request. TCF_RE 0 TCF interrupt requests are disabled 1 TCF interrupt requests are enabled 30–29 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-15...
Page 666: Dspi Push Tx Fifo Register (Dspi_Pushr)
Section 29.4.2.4, “TX FIFO Buffering Mechanism,” for more information. Write accesses of 8- or 16-bits to the DSPI_PUSHR transfer 32 bits to the TX FIFO. NOTE Only the TXDATA field is used for DSPI slaves. MCF52277 Reference Manual, Rev. 1 29-16 Freescale Semiconductor...
Page 667 DSPI_TCR[SPI_TCNT] field. The SPI_TCNT field is cleared before transmission of the current SPI frame begins. This bit is used only in SPI master mode. 0 Do not clear DSPI_TCR[SPI_TCNT] field 1 Clear DSPI_TCR[SPI_TCNT] field 25–24 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-17...
Page 668: Dspi Pop Rx Fifo Register (Dspi_Popr)
TX FIFO. The registers are read-only and cannot be modified. Reading the DSPI_TXFRn registers does not alter the state of TX FIFO. The 16-entry deep FIFO is implemented with 16 registers, DSPI_TXFR0–15. MCF52277 Reference Manual, Rev. 1 29-18 Freescale Semiconductor...
Page 669: Dspi Receive Fifo Registers 0–15 (Dspi_Rxfrn)
0xFC05_C0B8 (DSPI_RXFR15) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RXDATA Reset 0 Figure 29-10. DSPI_RXFRn Registers 0–15 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-19...
Page 670: Functional Description
The DSPI has two operating states; stopped and running. The default state of the DSPI is stopped. In the stopped state, no serial transfers are initiated in master mode and no transfers are responded to in slave MCF52277 Reference Manual, Rev. 1 29-20...
Page 671: Serial Peripheral Interface (Spi) Configuration
In master mode, the DSPI initiates and controls the transfer according to the SPI command field of the TX FIFO entry. In slave mode, the DSPI only responds to MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 672: Master Mode
DSPI_PUSHR, refer to Section 29.3.6, “DSPI PUSH TX FIFO Register (DSPI_PUSHR).” TX FIFO entries can only be removed from the TX FIFO by being shifted out or by flushing the TX FIFO. MCF52277 Reference Manual, Rev. 1 29-22 Freescale Semiconductor...
Page 673: Rx Fifo Buffering Mechanism
The RXCTR is updated every time the DSPI _POPR is read or SPI data is copied from the shift register to the RX FIFO. The DSPI_SR[POPNXTPTR] field points to the RX FIFO entry returned when the DSPI_POPR is read. The POPNXTPTR contains the positive, 32-bit word offset from DSPI_RXFR0. For example, MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-23...
Page 674: Dspi Baud Rate And Clock Delay Generation
BR fields in the DSPI_CTARn select the frequency of DSPI_SCK using the following formula: SYS/2 × Eqn. 29-1 SCK baud rate ------------------------------------------------- - --------------------------------------- - PBR Prescaler Value BR Scaler Value MCF52277 Reference Manual, Rev. 1 29-24 Freescale Semiconductor...
Page 675 DSPI_PCS signal for the next frame. See Figure 29-14 for an illustration of the delay after transfer. DSPI_CTARn[PDT, DT] fields select the delay after transfer by the formula: × × ------------ - Eqn. 29-4 SYS/2 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-25...
Page 676: Transfer Formats
In this format, the master and slave sample their DSPI_SIN pins on the odd-numbered DSPI_SCK edges and change the data on their DSPI_SOUT pins on the even-numbered DSPI_SCK edges. MCF52277 Reference Manual, Rev. 1 29-26 Freescale Semiconductor...
Page 677 DSPI_SCK edge before the first data bit becomes available on the slave DSPI_SOUT pin. In this format, the master and slave devices change the data on their DSPI_SOUT pins on the odd-numbered DSPI_SCK edges and sample the data on their DSPI_SIN pins on the even-numbered DSPI_SCK edges. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-27...
Page 678 SPI mode to allow for delays in device pads and board traces. These delays become a more significant fraction of the DSPI_SCK period as the DSPI_SCK period decreases with increasing baud rates. MCF52277 Reference Manual, Rev. 1 29-28 Freescale Semiconductor...
Page 679 Slave DSPI_SOUT Master DSPI_SOUT DSPI_PCSn System Clock System Clock = PCS to SCK delay. = After SCK delay. Figure 29-16. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, Fsck = Fsys/4) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-29...
Page 680: Continuous Selection Format
When CONT is cleared, DSPI drives the asserted chip select signals to their idle states in between frames. The idle states of the chip select signals are selected by the DSPI_MCR[PCSIS] field. Figure 29-18 shows the timing diagram for two four-bit transfers with CPHA set and CONT cleared. MCF52277 Reference Manual, Rev. 1 29-30 Freescale Semiconductor...
Page 681 The DSPI_PCSn signal must be negated before DSPI_CTAR is switched. When CONT is set and the DSPI_PCSn signals for the next transfer are different from the present transfer, the DSPI_PCSn signals behave as if the CONT bit was cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-31...
Page 682: Continuous Serial Communications Clock
Enabling continuous SCK disables the PCS to SCK delay and the after SCK delay. The delay after transfer is fixed at one DSPI_SCK cycle. Figure 29-21 shows timing diagram for continuous SCK format with continuous selection disabled. MCF52277 Reference Manual, Rev. 1 29-32 Freescale Semiconductor...
Page 683: Interrupts/Dma Requests
TX FIFO is not full TFFF Current frame transfer is complete — TX FIFO underflow has occurred TFUF — RX FIFO is not empty RFDF RX FIFO overflow has occurred RFOF — MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-33...
Page 684 TX FIFO of a DSPI operating in slave mode is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while the DSPI_RSER[TFUF_RE] bit is set, an interrupt request is generated. MCF52277 Reference Manual, Rev. 1 29-34 Freescale Semiconductor...
Page 685: Power Saving Features
Slave Interface Signal Gating The DSPI’s module enable signal gates slave interface signals such as address, byte enable, read/write and data. This prevents toggling slave interface signals from consuming power unless the DSPI is accessed. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-35...
Page 686: Initialization/Application Information
PBR and the baud rate scaler BR in the DSPI_CTARn registers. The values calculated assume a 100 MHz system frequency. MCF52277 Reference Manual, Rev. 1 29-36 Freescale Semiconductor...
Page 687: Delay Settings
) and CS to SCK delay (t ) that can be generated based on the prescaler values and the scaler values set in the DSPI_CTARn registers. The values calculated assume a 100 MHz system frequency. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-37...
Page 688: Calculation Of Fifo Pointer Addresses
TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO. See Section 29.4.2.4, “TX FIFO Buffering Mechanism,” Section 29.4.2.5, “RX FIFO Buffering Mechanism,” for details on the FIFO operation. MCF52277 Reference Manual, Rev. 1 29-38 Freescale Semiconductor...
Page 689 Last-in entry address = RX FIFO base + 4 × [(RXCTR + POPNXTPTR - 1) modulo RX FIFO depth] RX FIFO base: base address of RX FIFO RXCTR: RX FIFO counter POPNXTPTR: pop next pointer RX FIFO depth: 16 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 29-39...
Page 690 DMA Serial Peripheral Interface (DSPI) MCF52277 Reference Manual, Rev. 1 29-40 Freescale Semiconductor...
Page 691: Introduction
(to Interrupt Controller) Logic Programmable Internal Bus Clock (f Clock Transmit DMA Request sys/2 DMA Request Generation or External Clock (DTnIN) Receive DMA Request Logic (To DMA Controller) Figure 30-1. UART Block Diagram MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-1...
Page 692: Features
All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation • Detection of breaks originating in the middle of a character MCF52277 Reference Manual, Rev. 1 30-2 Freescale Semiconductor...
Page 693: External Signal Description
Writing control bytes into the appropriate registers controls the operation of the UART module. NOTE UART registers are accessible only as bytes. NOTE Interrupt can mean an interrupt request asserted to the CPU or a DMA request. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-3...
Page 694 UMR1n, UMR2n, and UCSRn must be changed only after the receiver/transmitter is issued a software reset command. If operation is not disabled, undesirable results may occur. Reading this register results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed. MCF52277 Reference Manual, Rev. 1 30-4 Freescale Semiconductor...
Page 695: Uart Mode Registers 1 (Umr1N)
Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 696: Uart Mode Register 2 (Umr2N)
Address: 0xFC06_0000 (UMR20) Access: User read/write 0xFC06_4000 (UMR21) 0xFC06_8000 (UMR22) TXRTS TXCTS Reset: After UMR1n is read or written, the pointer points to UMR2n Figure 30-4. UART Mode Registers 2 (UMR2n) MCF52277 Reference Manual, Rev. 1 30-6 Freescale Semiconductor...
Page 697: Uart Status Registers (Usrn)
1.438 0.938 1110 1.938 0111 1.500 1.000 1111 2.000 30.3.3 UART Status Registers (USRn) The USRn registers, shown in Figure 30-5, show the status of the transmitter, the receiver, and the FIFO. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-7...
Page 698 1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent. MCF52277 Reference Manual, Rev. 1 30-8 Freescale Semiconductor...
Page 699: Uart Clock Select Registers (Ucsrn)
30-7, supply commands to the UART. Only multiple commands that do not conflict can be specified in a single write to a UCRn. For example, RESET TRANSMITTER ENABLE cannot be specified in one command. TRANSMITTER MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-9...
Page 700 Transmitter must be enabled for the command to be accepted. This command ignores the state of UnCTS. Causes UnTXD to go high (mark) within two bit times. Any characters in the STOP BREAK transmit buffer are sent. MCF52277 Reference Manual, Rev. 1 30-10 Freescale Semiconductor...
Page 701: Uart Receive Buffers (Urbn)
FIFO. UnRXD is connected to the serial shift register. The CPU reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift register is full (see Figure 30-18). RB contains the character in the receiver. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-11...
Page 702: Uart Transmit Buffers (Utbn)
The UIPCRs, shown in Figure 30-10, hold the current state and the change-of-state for UnCTS. Address: 0xFC06_0010 (UIPCR0) Access: User read-only 0xFC06_4010 (UIPCR1) 0xFC06_8010 (UIPCR2) Reset: UnCTS Figure 30-10. UART Input Port Changed Registers (UIPCRn) MCF52277 Reference Manual, Rev. 1 30-12 Freescale Semiconductor...
Page 703: Uart Auxiliary Control Register (Uacrn)
If a UIMRn bit is cleared, state of the corresponding UISRn bit has no effect on the output. The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-13...
Page 704 0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TXRDY is cleared are not sent. 1 The transmitter holding register is empty and ready to be loaded with a character. MCF52277 Reference Manual, Rev. 1 30-14 Freescale Semiconductor...
Page 705: Uart Baud Rate Generator Registers (Ubg1N/Ubg2N)
The UIPn registers, shown in Figure 30-15, show the current state of the UnCTS input. Address: 0xFC06_0034 (UIP0) Access: User read-only 0xFC06_4034 (UIP1) 0xFC06_8034 (UIP2) Reset: Figure 30-15. UART Input Port Registers (UIPn) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-15...
Page 706: Uart Output Port Command Registers (Uop1N/Uop0N)
The internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each UART. The 16-bit divider is used to produce standard UART baud rates. MCF52277 Reference Manual, Rev. 1 30-16 Freescale Semiconductor...
Page 707 When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is: sys 2 ⁄ Baudrate ---------------------------------- - Eqn. 30-1 32 x divider MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-17...
Page 708: Transmitter And Receiver Operating Modes
UART sets USRn[TXRDY]. The transmitter converts parallel data from the CPU to a serial bit stream on UnTXD. It automatically sends a start bit followed by the programmed number of data bits, an MCF52277 Reference Manual, Rev. 1 30-18...
Page 709 The transmitter must be manually reenabled by reasserting UnRTS before the next message is sent. Figure 30-19 shows the functional timing information for the transmitter. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-19...
Page 710 (framing error) and UnRXD remains low for one-half of the bit period after the stop bit is sampled, receiver operates as if a new start bit were detected. Parity error, MCF52277 Reference Manual, Rev. 1 30-20...
Page 711 In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break (RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 712: Looping Modes
Section 30.3, “Memory Map/Register Definition.” The UART’s transmitter and receiver should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. MCF52277 Reference Manual, Rev. 1 30-22 Freescale Semiconductor...
Page 713: Automatic Echo Mode
Received parity is not checked and is not recalculated for transmission. Stop bits are sent as they are received. A received break is echoed as received until next valid start bit is detected. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 714: Multidrop Mode
Data fields in the data stream are separated by an address character. After a slave receives a block of data, its CPU disables the receiver and repeats the process. Functional timing information for multidrop mode is shown in Figure 30-24. MCF52277 Reference Manual, Rev. 1 30-24 Freescale Semiconductor...
Page 715 If 8-bit characters are not required, one way to provide error detection is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor...
Page 716: Bus Operation
Section 15.2.9.1, “Interrupt Sources,” for details on interrupt assignments for the UART modules. 1. Initialize the appropriate ICRx register in the interrupt controller. 2. Unmask appropriate bits in IMR in the interrupt controller. MCF52277 Reference Manual, Rev. 1 30-26 Freescale Semiconductor...
Page 717 The implementation described in this section allows independent DMA processing of transmit and receive data while continuing to support interrupt notification to the processor for CTS change-of-state and delta break error managing. Table 30-14 shows the DMA requests. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-27...
Page 718: Uart Module Initialization Sequence
Select the mode of operation (CM bits). b) If preferred, program operation of transmitter ready-to-send (TXRTS). c) If preferred, program operation of clear-to-send (TXCTS bit). d) Select stop-bit length (SB bits). 7. UCRn: Enable transmitter and/or receiver. MCF52277 Reference Manual, Rev. 1 30-28 Freescale Semiconductor...
Page 719 Enable Serial Module Errors? SINIT Initiate: Channel Enable Receiver Interrupts CHK1 Assert Request To Send Call CHCHK SINITR Return Save Channel Status Figure 30-25. UART Mode Programming Flowchart (Sheet 1 of 5) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-29...
Page 720 Transmitter Never-ready Flag Too Long? Ready? SNDCHR Send Character To Transmitter RxCHK Waited Set Receiver- Character Been Too Long? Never-ready Flag Received? Figure 30-25. UART Mode Programming Flowchart (Sheet 2 of 5) MCF52277 Reference Manual, Rev. 1 30-30 Freescale Semiconductor...
Page 721 PRCHK Have Return Parity Error? Set Parity Error Flag CHRCHK Get Character From Receiver Same As Transmitted Character? Set Incorrect Character Flag Figure 30-25. UART Mode Programming Flowchart (Sheet 3 of 5) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-31...
Page 722 Clear Change-in- Break Status Bit Remove Break Character From Receiver FIFO Replace Return Address On System Stack And Monitor Warm Start Address SIRQR Figure 30-25. UART Mode Programming Flowchart (Sheet 4 of 5) MCF52277 Reference Manual, Rev. 1 30-32 Freescale Semiconductor...
Page 723 UART Modules OUTCH Transmitter Ready? Send Character To Transmitter Return Figure 30-25. UART Mode Programming Flowchart (Sheet 5 of 5) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 30-33...
Page 724 UART Modules MCF52277 Reference Manual, Rev. 1 30-34 Freescale Semiconductor...
Page 725: Introduction
Register Start, Stop, Arbitration Control Input Address Sync Compare I2C_SCL I2C_SDA Figure 31-1. I C Module Block Diagram Figure 31-1 shows the I C registers, described in Section 31.2, “Memory Map/Register Definition”: MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 31-1...
Page 726: Overview
Software-programmable for one of 50 different serial clock frequencies • Software-selectable acknowledge bit • Interrupt-driven, byte-by-byte data transfer • Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt MCF52277 Reference Manual, Rev. 1 31-2 Freescale Semiconductor...
Page 727: Memory Map/Register Definition
Reserved, must be cleared. 31.2.2 C Frequency Divider Register (I2FDR) The I2FDR, shown in Figure 31-3, provides a programmable prescaler to configure the I C clock for bit-rate selection. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 31-3...
Page 728 0x3F 2048 31.2.3 C Control Register (I2CR) The I2CR enables the I C module and the I C interrupt. It also contains bits that govern operation as a slave or a master. MCF52277 Reference Manual, Rev. 1 31-4 Freescale Semiconductor...
Page 729 Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration. RSTA 0 No repeat start 1 Generates a repeated START condition. 1–0 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 31-5...
Page 730 Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle. RXAK 0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus 1 No acknowledge signal was detected at the ninth clock. MCF52277 Reference Manual, Rev. 1 31-6 Freescale Semiconductor...
Page 731: Functional Description
31-7). A START signal is defined as a high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 31-7...
Page 732: Slave Address Transmission
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Slave Address Data Byte STOP ACK from START ACK Bit Signal Receiver Signal Figure 31-8. Data Transfer MCF52277 Reference Manual, Rev. 1 31-8 Freescale Semiconductor...
Page 733: Acknowledge
Figure 31-10. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 31-9...
Page 734 Note: No acknowledge on the last byte Example 3: 7-bit Slave Rept 7-bit Slave Data Data Data Address Address Master Writes to Slave Master Reads from Slave Figure 31-11. Data Transfer, Combined Format MCF52277 Reference Manual, Rev. 1 31-10 Freescale Semiconductor...
Page 735: Clock Synchronization And Arbitration
STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration. I2C_SCL I2C_SDA by Master1 I2C_SDA by Master 2 Loses Arbitration, Master2 and becomes slave-receiver I2C_SDA Figure 31-13. Arbitration Procedure MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 31-11...
Page 736: Handshaking And Clock Stretching
The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the I2C_SCL period, the MCF52277 Reference Manual, Rev. 1 31-12...
Page 737: Post-Transfer Software Response
2. Get value from transmitting counter, TXCNT. If no more data, go to step #5. 3. Transmit next byte of data via I2DR. 4. Decrement TXCNT and go to step #1 5. Generate a stop condition by clearing I2CR[MSTA]. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 31-13...
Page 738: Generation Of Repeated Start
MSTA without signaling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, slave service routine should first test IAL and software should clear it if it is set. MCF52277 Reference Manual, Rev. 1 31-14 Freescale Semiconductor...
Page 739 Rx Mode Mode Read Data Generate Dummy Read Dummy Read Dummy Read from I2DR from I2DR STOP Signal from I2DR from I2DR And Store Figure 31-14. Flow-Chart of Typical I C Interrupt Routine MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 31-15...
Page 740 C Interface MCF52277 Reference Manual, Rev. 1 31-16 Freescale Semiconductor...
Page 741: Introduction
External development systems can access saved data, because the hardware supports concurrent operation of the processor and BDM-initiated commands. In addition, the option allows interrupts to occur. See Section 32.6, “Real-Time Debug Support”. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-1...
Page 742: Signal Descriptions
Halt status is reflected on processor status signals (PST[3:0]) as the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the processor. MCF52277 Reference Manual, Rev. 1 32-2 Freescale Semiconductor...
Page 743: Real-Time Trace Support
(lsb). Execution speed is affected only when both storage elements contain valid data to be dumped to the DDATA port. The core stalls until one FIFO entry is available. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-3...
Page 744: Begin Execution Of Taken Branch (Pst = 0X5)
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed on DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, MCF52277 Reference Manual, Rev. 1 32-4...
Page 745: Memory Map/Register Definition
These registers are also accessible from the processor’s supervisor programming model by executing the WDEBUG instruction (write only). Therefore, the breakpoint hardware in debug module can be read or MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-5...
Page 746 BDM port using the command. In addition, the WDMREG configuration/status register (CSR) can be read through the BDM port using command. RDMREG MCF52277 Reference Manual, Rev. 1 32-6 Freescale Semiconductor...
Page 747: Shared Debug Resources
0x00 using the WDEBUG instruction and through the BDM port using the RDMREG WDMREG commands. DRc[4:0]: 0x00 (CSR) Access: Supervisor write-only BDM read/write BSTAT TRG HALT BKPT Reset FDBG DBGH Reset Figure 32-3. Configuration/Status Register (CSR) MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-7...
Page 748 TM equals 101 or 110. The internal SRAM and caches are disabled. Force emulation mode on trace exception. 0 The processor enters supervisor mode 1 The processor enters emulator mode when a trace exception occurs MCF52277 Reference Manual, Rev. 1 32-8 Freescale Semiconductor...
Page 749 1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed. On receipt of the command, the processor executes the next instruction and halts again. This process continues until SSM is cleared. 3–2 Reserved, must be cleared. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-9...
Page 750: Bdm Address Attribute Register (Baar)
Transfer Type. See the TT definition in the AATR description, Section 32.4.4, “Address Attribute Trigger Register (AATR)”. 2–0 Transfer Modifier. See the TM definition in the AATR description, Section 32.4.4, “Address Attribute Trigger Register (AATR)”. MCF52277 Reference Manual, Rev. 1 32-10 Freescale Semiconductor...
Page 751: Address Attribute Trigger Register (Aatr)
Transfer Modifier Mask. Setting a TMM bit masks the corresponding TM bit in address comparisons. Read/Write. R is compared with the R/W signal of the processor’s local bus. 6–5 Size. Compared to the processor’s local bus size signals. 00 Longword 01 Byte 10 Word 11 Reserved MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-11...
Page 752: Trigger Definition Register (Tdr)
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command. MCF52277 Reference Manual, Rev. 1 32-12 Freescale Semiconductor...
Page 753 Level 2 Data Breakpoint Invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a L2DI trigger based on the occurrence of a data value other than the DBR contents. 0 No inversion 1 Invert data breakpoint comparators. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-13...
Page 754 Note: Debug Rev A only had the AND condition available for the triggers. Enable Level 1 Breakpoint. Global enable for the breakpoint trigger. L1EBL 0 Disables all level 1 breakpoints 1 Enables all level 1 breakpoint triggers MCF52277 Reference Manual, Rev. 1 32-14 Freescale Semiconductor...
Page 755: Program Counter Breakpoint/Mask Registers (Pbr0–3, Pbmr)
PBR1–3) and TDR is configured appropriately. PBR0 bits are masked by setting corresponding PBMR bits (PBMR has no effect on PBR1–3). Results are compared with the processor’s program counter register, as defined in TDR. Breakpoint registers, PBR1–3, have no masking associated with them. The MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-15...
Page 756 0 PBR is disabled. 1 PBR is enabled. Figure 32-9 shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and via the BDM port using the command. PBMR only masks PBR0. WDMREG MCF52277 Reference Manual, Rev. 1 32-16 Freescale Semiconductor...
Page 757: Address Breakpoint Registers (Ablr, Abhr)
Address specific single addresses are programmed into ABLR. Table 32-14. ABHR Field Description Field Description 31–0 High Address. Holds the 32-bit address marking the upper bound of the address breakpoint range. Address MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-17...
Page 758: Data Breakpoint And Mask Registers (Dbr, Dbmr)
DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a DBMR bit causes that bit to be ignored. The DBR supports aligned and misaligned references. Table 32-17 shows relationships between processor address, access size, and location within the 32-bit data bus. MCF52277 Reference Manual, Rev. 1 32-18 Freescale Semiconductor...
Page 759: Background Debug Mode (Bdm)
BKPT. This type of halt is always first marked as pending in the pocessor, which samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point. See Section 32.6.1, “Theory of Operation”. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-19...
Page 760: Bdm Serial Interface
17-bit packets composed of a status/control bit and a 16-bit data word. As shown Figure 32-13, all state transitions are enabled on a rising edge of the PSTCLK clock when DSCLK is high; DSI is sampled and DSO is driven. MCF52277 Reference Manual, Rev. 1 32-20 Freescale Semiconductor...
Page 761: Receive Packet Format
Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 32.5.2.1 Receive Packet Format The basic receive packet consists of 16 data bits and 1 status bit Data Figure 32-14. Receive BDM Packet MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-21...
Page 762: Bdm Command Set
BDM command set. Subsequent paragraphs contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior. See Table 32-22 for register address encodings. MCF52277 Reference Manual, Rev. 1 32-22 Freescale Semiconductor...
Page 763 - Parallel: Command is executed in parallel with CPU activity. 0x4 is a three-bit field. Freescale reserves unassigned command opcodes. All unused command formats within any revision level perform a and return the illegal command response. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-23...
Page 764: Coldfire Bdm Command Format
Operands and addresses are transferred most-significant word first. In the following descriptions of the BDM command set, the optional set of extension words is defined as address, data, or operand data. MCF52277 Reference Manual, Rev. 1 32-24 Freescale Semiconductor...
Page 765: Command Sequence Diagrams
• At the completion of cycle 3, the debug module initiates a memory read operation. Any serial transfers that begin during a memory access return a not-ready response. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-25...
Page 766: Command Set Descriptions
LS RESULT NEXT CMD BERR ’NOT READY’ Figure 32-19. Command Sequence RAREG RDREG Operand Data: None Result Data: The contents of the selected register are returned as a longword value, most-significant word first. MCF52277 Reference Manual, Rev. 1 32-26 Freescale Semiconductor...
Page 767 Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-27...
Page 768 Word results return 16 bits of data; longword results return 32. Bytes are returned in the LSB of a word result; the upper byte is undefined. 0x0001 (S = 1) is returned if a bus error occurs. MCF52277 Reference Manual, Rev. 1 32-28 Freescale Semiconductor...
Page 769 Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Command Formats: Byte A[31:16] A[15:0] D[7:0] Word A[31:16] A[15:0] D[15:0] Longword A[31:16] A[15:0] D[31:16] D[15:0] Figure 32-24. Command Format WRITE MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-29...
Page 770 The initial address increments by the operand size (1, 2, or 4) and saves in a temporary register. Subsequent commands use this address, perform the memory read, increment it by the current DUMP operand size, and store the updated address in the temporary register. MCF52277 Reference Manual, Rev. 1 32-30 Freescale Semiconductor...
Page 771 DUMP (LONG) MEMORY ’NOT READY’ LOCATION NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD NEXT CMD ’ILLEGAL’ ’NOT READY’ BERR ’NOT READY’ Figure 32-27. Command Sequence DUMP Operand Data: None MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-31...
Page 772 The size field is examined each time a command is processed, allowing the operand size to be altered FILL dynamically. Command Formats: Byte D[7:0] Word D[15:0] Longword D[31:16] D[15:0] Figure 32-28. Command Format FILL MCF52277 Reference Manual, Rev. 1 32-32 Freescale Semiconductor...
Page 773 BDM command while the processor is halted, the updated value is used when prefetching resumes. If a command issues and the CPU is not halted, the command is ignored. Figure 32-30. Command Format Command Sequence: NEXT CMD ’CMD COMPLETE’ Figure 32-31. Command Sequence MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-33...
Page 774 PC for performance monitoring. The SYNC execution of this command is considerably less obtrusive to the real-time operation of an application than command sequence. HALT READ RESUME Command Formats: MCF52277 Reference Manual, Rev. 1 32-34 Freescale Semiconductor...
Page 775 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same the processor’s MOVEC instruction uses. Command/Result Formats: Command Result D[31:16] D[15:0] Figure 32-36. Command/Result Formats RCREG MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-35...
Page 776 MAC Accumulator 2,3 Extension Bytes (ACCEXT23) 0x809 MAC Accumulator 1 (ACC1) 0x80A MAC Accumulator 2 (ACC2) 0x80B MAC Accumulator 3 (ACC3) 0x80E Status Register (SR) 0x80F Program Register (PC) 0xC05 RAM Base Address Register (RAMBAR) MCF52277 Reference Manual, Rev. 1 32-36 Freescale Semiconductor...
Page 777 The operand (longword) data is written to the specified control register. The write alters all 32 register bits. See the RCREG instruction description for the Rc encoding and for additional notes on writes to the A7 stack pointers and the EMAC programming model. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-37...
Page 778 RDMREG command is CSR (DRc = 0x00). This read of the CSR clears CSR (FOF, TRG, HALT, and BKPT) as well as the trigger status bits (CSR[BSTAT]) if a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and no level-2 breakpoint has been enabled. Command/Result Formats: MCF52277 Reference Manual, Rev. 1 32-38 Freescale Semiconductor...
Page 779 The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-39...
Page 780: Real-Time Debug Support
As shown in Table 32-24, when a breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status, operands, or branch addresses. MCF52277 Reference Manual, Rev. 1 32-40 Freescale Semiconductor...
Page 781 The debug interrupt handler can use supervisor instructions to save the necessary context, such as the state of all program-visible registers into a reserved memory area. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-41...
Page 782: Concurrent Bdm And Processor Operation
After the debug module bus cycle, the processor reclaims the bus. MCF52277 Reference Manual, Rev. 1 32-42 Freescale Semiconductor...
Page 783: Processor Status, Debug Data Definition
In this definition, the y suffix generally denotes the source, and x denotes the destination operand. For a given instruction, the optional operand data is displayed only for those effective addresses referencing memory. The DD nomenclature refers to the DDATA outputs. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-43...
Page 784 PST = 0x1, {PST = 0xB, DD = source operand} divs.w <ea>y,Dx PST = 0x1, {PST = 0x9, DD = source operand} divu.l <ea>y,Dx PST = 0x1, {PST = 0xB, DD = source operand} MCF52277 Reference Manual, Rev. 1 32-44 Freescale Semiconductor...
Page 785 PST = 0x1, {PST = 0x9, DD = source operand} neg.l PST = 0x1 negx.l PST = 0x1 PST = 0x1 not.l PST = 0x1 or.l <ea>y,Dx PST = 0x1, {PST = 0xB, DD = source operand} MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-45...
Page 786 PST = 0x4, {PST = 0x8, DD = source operand wddata.l <ea>y PST = 0x4, {PST = 0xB, DD = source operand wddata.w <ea>y PST = 0x4, {PST = 0x9, DD = source operand MCF52277 Reference Manual, Rev. 1 32-46 Freescale Semiconductor...
Page 787 PST = 0x1 move.l {Ry,#<data>},ACCext23 PST = 0x1 move.l ACCext01,Rx PST = 0x1 move.l ACCext23,Rx PST = 0x1 move.l ACCy,ACCx PST = 0x1 move.l ACCy,Rx PST = 0x1 move.l MACSR,CCR PST = 0x1 MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-47...
Page 788: Supervisor Instruction Set
Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state (PST = 0xFF) display this status throughout the entire time the ColdFire processor is in the given mode. MCF52277 Reference Manual, Rev. 1 32-48...
Page 789: Freescale-Recommended Bdm Pinout
Developer reserved RESET EVDD PST3 PST2 PST1 PST0 DDATA3 DDATA1 DDATA2 DDATA0 Freescale reserved Freescale reserved PSTCLK IVDD Pins reserved for BDM developer use. Supplied by target Figure 32-44. Recommended BDM Connector MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 32-49...
Page 790 Debug Module MCF52277 Reference Manual, Rev. 1 32-50 Freescale Semiconductor...
Page 791: Introduction
1-bit TEST_CTRL Register 5-bit TAP Instruction Decoder 5-bit TAP Instruction Register JTAG_EN TCLK Disable DSCLK TMS/BKPT Force BKPT = 1 TRST/DSCLK JTAG Module to Debug Module BKPT DSCLK Figure 33-1. JTAG Block Diagram MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 33-1...
Page 792: Features
The JTAG_EN pin selects between the debug module and JTAG. If JTAG_EN is low, the debug module is selected; if it is high, the JTAG is selected. Table 33-2 summarizes the pin function selected depending on JTAG_EN logic state. MCF52277 Reference Manual, Rev. 1 33-2 Freescale Semiconductor...
Page 793: Test Clock Input (Tclk)
The TDI pin receives serial test and data, which is sampled on the rising edge of TCLK. Register values are shifted in least significant bit (lsb) first. The TDI pin has an internal pull-up resistor. The DSI pin provides data input for the debug module serial communication port. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 33-3...
Page 794: Test Reset/Development Serial Clock (Trst/Dsclk)
TDO pin. See Section 33.4.3, “JTAG Instructions” for a list of possible instruction codes. TAP state: Update-IR Access: User read/write Instruction Code Reset Figure 33-2. 5-Bit Instruction Register (IR) MCF52277 Reference Manual, Rev. 1 33-4 Freescale Semiconductor...
Page 795: Idcode Register
ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold register on the rising edge of TCLK when the TAP state machine is in the update-DR state. The DSE bit selects the drive strength used in JTAG mode. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 33-5...
Page 796: Boundary Scan Register
Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state. As Figure 33-5 shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state. MCF52277 Reference Manual, Rev. 1 33-6 Freescale Semiconductor...
Page 797: Jtag Instructions
Selects IDCODE register for shift SAMPLE/PRELOAD 00010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 00011 Selects boundary scan register for shifting and sampling without disturbing functional operation MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 33-7...
Page 798: Idcode Instruction
IR contains the 0x2 opcode. The sampled data is accessible by shifting it through the boundary scan register to the TDO output by using the shift-DR state. The data capture and the shift operation are transparent to system operation. MCF52277 Reference Manual, Rev. 1 33-8 Freescale Semiconductor...
Page 799: Highz Instruction
Therefore, the first bit shifted out after selecting the bypass register is always logic 0. This differentiates parts that support an IDCODE register from parts that support only the bypass register. MCF52277 Reference Manual, Rev. 1 Freescale Semiconductor 33-9...
Page 800: Initialization/Application Information
However, because there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST. MCF52277 Reference Manual, Rev. 1 33-10 Freescale Semiconductor...

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