Freescale Semiconductor MCF54455 Reference Manual page 666

Fast Ethernet Controllers (FEC0 and FEC1)
26.5.17.1.2 Retransmission Attempts Limit Expired
When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are flushed
and closed, and EIRn[RL] is set. The FEC then continues to the next transmit buffer descriptor and begins
transmitting the next frame. The RL interrupt is asserted if enabled in the EIMRn register.
26.5.17.1.3 Late Collision
When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates
transmission. All remaining buffers for that frame are flushed and closed, and EIRn[LC] is set. The FEC
then continues to the next transmit buffer descriptor and begin transmitting the next frame. The LC
interrupt is asserted if enabled in the EIMRn register.
26.5.17.1.4 Heartbeat
Some transceivers have a self-test called heartbeat or signal quality error. To signify a good self-test, the
transceiver indicates a collision to the FEC within four microseconds after completion of a frame
transmitted by the Ethernet controller. This indication of a collision does not imply a real collision error
on the network, but is rather an indication that the transceiver continues to function properly. This is the
heartbeat condition.
If TCRn[HBC] is set and the heartbeat condition is not detected by the FEC after a frame transmission, a
heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets EIRn[HB], and generates
the HBERR interrupt if it is enabled.
26.5.17.2 Reception Errors
26.5.17.2.1 Overrun Error
If the receive block has data to put into the receive FIFO and the receive FIFO is full, FEC sets
RxBDn[OV]. All subsequent data in the frame is discarded and subsequent frames may also be discarded
until the receive FIFO is serviced by the DMA and space is made available. At this point the receive
frame/status word is written into the FIFO with the OV bit set. The driver must discard this frame.
26.5.17.2.2 Non-Octet Error (Dribbling Bits)
The Ethernet controller manages up to seven dribbling bits when the receive frame terminates past an
non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error, the
frame non-octet aligned (NO) error is reported in the RxBDn. If there is no CRC error, no error is reported.
26.5.17.2.3 CRC Error
When a CRC error occurs with no dribble bits, FEC closes the buffer and sets RxBDn[CR]. CRC checking
cannot be disabled, but the CRC error can be ignored if checking is not required.
26.5.17.2.4 Frame Length Violation
When the receive frame length exceeds MAX_FL bytes the BABR interrupt is generated, and RxBDn[LG]
is set. The frame is not truncated unless the frame length exceeds 2047 bytes.
Freescale Semiconductor 26-48