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Field
PSDR_x
Port x set data bits.
(write)
0 No effect.
1 Set corresponding PODR_x bit.
Note: See above figures for bit field positions.
16.3.4
Port Clear Output Data Registers (PCLRR_x)
Clearing a PCLRR_x register clears the corresponding bits in the PODR_x register. Setting it has no effect.
Reading the PCLRR_x register returns zeroes. The PCLRR_x registers are each eight bits wide, but not all
ports use all eight bits. The register definitions for all ports are shown in the figures below.
Address: 0xFC0A_4048 (PCLRR_FEC0H)
0xFC0A_4049 (PCLRR_FEC0L)
0xFC0A_4051 (PCLRR_UART)
0xFC0A_4054 (PCLRR_PCI)
0xFC0A_4058 (PCLRR_FEC1H)
0xFC0A_4059 (PCLRR_FEC1L)
0xFC0A_405C (PCLRR_FBADH)
0xFC0A_405D (PCLRR_FBADMH)
0xFC0A_405E (PCLRR_FBADML)
0xFC0A_405F (PCLRR_FBADL)
7
R
0
W
Reset:
0
Figure 16-26. Port x Clear Output Data Registers (PCLRR_x)
Address: 0xFC0A_4052 (PCLRR_DSPI)
7
R
0
W
Reset:
0
Figure 16-27. Port DSPI Clear Output Data Registers (PCLRR_DSPI)
Freescale Semiconductor
Table 16-7. PPDSDR_x Field Descriptions (continued)
6
5
0
0
0
0
6
5
0
0
0
0
Description
4
3
2
0
0
0
PCLRR_x
0
0
0
4
3
2
0
0
0
PCLRR_DSPI
0
0
0
Pin Multiplexing and Control
Access: User write-only
1
0
0
0
0
0
Access: User write-only
1
0
0
0
0
0
16-23
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