Freescale Semiconductor MCF54455 Reference Manual page 776

31.4.2.1 Master Mode
In master mode, the DSPI initiates the serial transfers by controlling the serial communications clock
(DSPI_SCK) and the peripheral chip select (DSPI_PCSn) signals. The SPI command field in the executing
TX FIFO entry determines which DSPI_CTARn register sets the transfer attributes and which DSPI_PCSn
signal to assert. The command field also contains various bits that help with queue management and
transfer protocol. See Section 31.3.6, "DSPI Push Transmit FIFO Register (DSPI_PUSHR),"
on the SPI command fields. The data field in the executing TX FIFO entry is loaded into the shift register
and shifted out on the serial out (DSPI_SOUT) pin. In master mode, each SPI frame to be transmitted has
a command associated with it allowing for transfer attribute control on a frame by frame basis.
31.4.2.2 Slave Mode
In slave mode, the DSPI responds to transfers initiated by an SPI bus master. The DSPI does not initiate
transfers. Certain transfer attributes such as clock polarity, clock phase, and frame size must be set for
successful communication with an SPI master. The slave mode transfer attributes are set in the
DSPI_CTAR0 register.
31.4.2.3 FIFO Disable Operation
The FIFO disable mechanisms allow SPI transfers without using the TX or RX FIFOs. The DSPI operates
as a double-buffered simplified SPI when the FIFOs are disabled. The FIFOs are disabled separately;
setting the DSPI_MCR[DIS_TXF] bit disables the TX FIFO, and setting the DSPI_MCR[DIS_RXF] bit
disables the RX FIFO.
The FIFO disable mechanisms are transparent to the user and to host software; transmit data and
commands are written to the DSPI_PUSHR and received data is read from the DSPI_POPR. When the TX
FIFO is disabled, DSPI_SR[TFFF, TFUF, and TXCTR] fields behave as if there is a one-entry FIFO, but
the contents of DSPI_TXFRs and TXNXTPTR are undefined. Likewise, when RX FIFO is disabled,
DSPI_SR[RFDF, RFOF, and RXCTR] fields behave as if there is a one-entry FIFO, but the contents of
DSPI_RXFRs and POPNXTPTR are undefined.
The TX and RX FIFOs should be disabled only if the application's operating mode requires FIFO to be
disabled. A FIFO must be disabled before it is accessed. Failure to disable a FIFO prior to a first FIFO
access is not supported and may result in incorrect results.
When the FIFOs are disabled, the respective
DSPI_MCR[CLR_TXF, CLR_RXF] bits have no effect.
31.4.2.4 TX FIFO Buffering Mechanism
The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX FIFO holds
16 entries, each consisting of a command field and a data field. SPI commands and data are added to the
TX FIFO by writing to the DSPI push TX FIFO register (DSPI_PUSHR). For more information on
DSPI_PUSHR, refer to Section 31.3.6, "DSPI Push Transmit FIFO Register (DSPI_PUSHR)."
entries can only be removed from the TX FIFO by being shifted out or by flushing the TX FIFO.
Freescale Semiconductor
NOTE
DMA Serial Peripheral Interface (DSPI)
for details
TX FIFO
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