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Because this device shares the FlexBus signals with the PCI controller, these signal directions are only
valid when the FlexBus controls them. The directions may change during PCI cycles.
20.2.1
Address and Data Buses (FB_An, FB_Dn, FB_ADn)
In non-multiplexed mode, the FB_An and FB_Dn buses carry the address and data, respectively. The
number of byte lanes carrying the data is determined by the port size associated with the matching chip
select.
In multiplexed mode, the FB_ADn bus carries the address and data. The full
the first clock of a bus cycle (address phase). Following the first clock, the data is driven on the bus (data
phase). During the data phase, the address continues driving on the pins not used for data. For example, in
16-bit mode the address continues driving on FB_AD[
driving on FB_AD[
: ].
23 0
In non-multiplexed mode, the FB_AD[31:0] signals carry the data and the PCI address/data bus carries the
address. As a result, the PCI is disabled when the FlexBus operates in non-multiplexed mode.
Multiplexed/non-multiplexed operation is determined at reset by FB_AD[7:5]. See
Configuration Module (CCM),"
Because this device shares the FlexBus signals with the PCI controller, these signals tristate between bus
cycles.
20.2.2
Chip Selects (FB_CS[5:0])
The chip-select signal indicates which device is selected. A particular chip-select asserts when the transfer
address is within the device's address space, as defined in the base- and mask-address registers. The actual
number of chip selects available depends upon the pin configuration.
20.2.3
Byte Enables/Byte Write Enables (FB_BE/BWE[3:0])
When driven low, the byte enable (FB_BE/BWE[3:0]) outputs indicate data is to be latched or driven onto
a byte of the data bus. FB_BE/BWEn signals are asserted only to the memory bytes used during read or
write accesses. A configuration option is provided to assert these signals on reads and writes (byte enable)
or writes only (byte-write enable).
The FB_BE/BWEn signals are asserted during accesses to on-chip peripherals but not to on-chip SRAM
or cache. For external SRAM or flash devices, the FB_BE/BWEn outputs must be connected to individual
byte strobe signals.
20.2.4
Output Enable (FB_OE)
The output enable signal (FB_OE) is sent to the interfacing memory and/or peripheral to enable a read
transfer. FB_OE is only asserted during read accesses when a chip select matches the current address
decode.
Freescale Semiconductor
15 0
for more information.
32
-bit address is driven on
:
] and in 8-bit mode the address continues
FlexBus
Chapter 11, "Chip
20-3
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