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Manuals and User Guides for Freescale Semiconductor e200z3. We have
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Freescale Semiconductor e200z3 manual available for free PDF download: Reference Manual
Freescale Semiconductor e200z3 Reference Manual (442 pages)
Power Architecture Core
Brand:
Freescale Semiconductor
| Category:
Computer Hardware
| Size: 5 MB
Table of Contents
Table of Contents
3
Paragraph Page
4
Number Title Number
4
General Information
28
Related Documentation
29
Terminology Conventions
30
Acronyms and Abbreviations
30
Chapter 1 E200Z335 Core Complex Overview
33
Overview of the E200Z3 and E200Z335
33
Features
36
Programming Model
37
Register Set
37
Instruction Set
39
VLE Category
40
Interrupts and Exception Handling
40
Interrupt Handling
41
Interrupt Classes
41
Interrupt Types
42
Interrupt Registers
42
Microarchitecture Summary
44
Instruction Unit Features
45
Integer Unit Features
45
Load/Store Unit (LSU) Features
45
Memory Management Unit (MMU) Features
46
System Bus (Core Complex Interface) Features
46
Nexus 32+ Module Features
46
Legacy Support of Powerpc Architecture
46
Instruction Set Compatibility
47
User Instruction Set
47
Supervisor Instruction Set
47
Memory Subsystem
47
Interrupt Handling
47
Memory Management
48
Reset
48
Little-Endian Mode
48
Chapter 2
52
Powerpc Book E Registers
52
E200Z3-Specific Registers
54
E200Z3-Specific Device Control Registers
55
Processor Control Registers
55
Machine State Register (MSR)
55
Processor ID Register (PIR)
57
Processor Version Register (PVR)
58
System Version Register (SVR)
58
Registers for Integer Operations
59
General-Purpose Registers (Gprs)
59
Integer Exception Register (XER)
59
Registers for Branch Operations
60
Condition Register (CR)
60
CR Setting for Integer Instructions
62
CR Setting for Store Conditional Instructions
62
CR Setting for Compare Instructions
62
Count Register (CTR)
63
Link Register (LR)
63
SPE and SPFP APU Registers
64
Signal Processing/Embedded Floating-Point Status and Control Register (SPEFSCR)
64
Signal Processing and Embedded Floating-Point Status and Control
64
Register (SPEFSCR)
64
Accumulator (ACC)
67
Interrupt Registers
67
Interrupt Registers Defined by Book E
67
Save/Restore Register 0 (SRR0)
68
Save/Restore Register 1 (SRR1)
68
Critical Save/Restore Register 0 (CSRR0)
68
Critical Save/Restore Register 1 (CSRR1)
69
Data Exception Address Register (DEAR)
69
Interrupt Vector Prefix Register (IVPR)
69
Interrupt Vector Offset Registers (Ivors)
70
Exception Syndrome Register (ESR)
71
VLE Mode Instruction Syndrome
73
Misaligned Instruction Fetch Syndrome
73
Precise External Termination Error Syndrome
73
E200Z3-Specific Interrupt Registers
74
Debug Save/Restore Register 0 (DSRR0)
74
Debug Save/Restore Register 1 (DSRR1)
74
Machine Check Syndrome Register (MCSR)
74
Software-Use Sprs (SPRG0-SPRG7 and USPRG0)
75
Timer Registers
76
Timer Control Register (TCR)
77
Timer Status Register (TSR)
78
Time Base (TBU and TBL)
79
Decrementer Register
81
Decrementer Auto-Reload Register (DECAR)
81
Decrementer Register (DEC)
81
Debug Registers
82
Debug Address and Value Registers
82
Instruction Address Compare Registers (IAC1-IAC4)
82
Data Address Compare Registers (DAC1-DAC2)
83
Data Value Compare Registers (DVC1-DVC2) (E200Z335 Only)
83
Debug Counter Register (DBCNT)
84
Debug Control and Status Registers (DBCR0-DBCR3)
84
Debug Control Register 0 (DBCR0)
84
Debug Control Register 1 (DBCR1)
87
Debug Control Register 2 (DBCR2)
89
Debug Control Register 3 (DBCR3)
91
Debug Control Register 4 (DBCR4) (E200Z335 Only)
96
Debug Status Register (DBSR)
97
Debug External Resource Control Register (DBERC0)
98
Hardware Implementation-Dependent Registers
105
Hardware Implementation-Dependent Register 0 (HID0)
105
Hardware Implementation-Dependent Register 1 (HID1)
107
Branch Target Buffer (BTB) Registers
109
Branch Unit Control and Status Register (BUCSR)
109
L1 Cache Configuration Registers
109
L1 Cache Configuration Register 0 (L1CFG0)
109
MMU Registers
110
MMU Control and Status Register 0 (MMUCSR0)
110
MMU Configuration Register (MMUCFG)
110
TLB Configuration Registers (Tlbncfg)
111
TLB Configuration Register 0 (TLB0CFG)
111
TLB Configuration Register 1 (TLB1CFG)
112
MMU Assist Registers (MAS0-MAS4, MAS6)
113
Process ID Register (PID0)
117
Support for Fast Context Switching
117
Context Control Register (CTXCR)
118
SPR Register Access
118
Invalid SPR References
118
Synchronization Requirements for Sprs
118
Special-Purpose Register Summary
119
Reset Settings
122
Parallel Signature Unit Registers
124
Parallel Signature Control Register (PSCR)
125
Parallel Signature Status Register (PSSR)
126
Parallel Signature High Register (PSHR)
126
Parallel Signature Low Register (PSLR)
127
Parallel Signature Counter Register (PSCTR)
127
Parallel Signature Update High Register (PSUHR)
128
Parallel Signature Update Low Register (PSULR)
128
Chapter 3 Instruction Model
129
Operand Conventions
129
Data Organization in Memory and Data Transfers
129
Alignment and Misaligned Accesses
129
E200Z3 Floating-Point Implementation
130
Unsupported Instructions and Instruction Forms
130
3.3 Optionally Supported Instructions and Instruction Forms
130
3.4 Implementation-Specific Instructions
131
3.5 Booke Instruction Extensions
131
3.6 Memory Access Alignment Support
132
Memory Synchronization and Reservation Instructions
132
Branch Prediction
133
Interruption of Instructions by Interrupt Requests
133
E200Z3-Specific Instructions
134
Integer Select APU
134
Debug APU
134
Wait APU (E200Z335 Only)
134
Volatile Context Save/Restore APU (E200Z335 Only)
135
SPE APU Instructions
135
Embedded Vector and Scalar Single-Precision Floating-Point APU Instructions
143
Options for Embedded Floating-Point APU Implementations
144
Unimplemented Sprs and Read-Only Sprs
144
Invalid Instruction Forms
145
Instruction Summary
145
Instruction Index Sorted by Mnemonic
146
Instruction Index Sorted by Opcode
157
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