Edma Interrupt Request Register (Edma_Int) - Freescale Semiconductor MCF54455 Reference Manual

19.4.13 eDMA Interrupt Request Register (EDMA_INT)

The EDMA_INT provide a bit map for the 16 channels signaling the presence of an interrupt request for
each channel. Depending on the appropriate bit setting in the transfer-control descriptions, the eDMA
engine generates an interrupt a data transfer completion. The outputs of this register are directly routed to
the interrupt controller (INTC). During the interrupt-service routine associated with any given channel, it
is the software's responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write
to the EDMA_CINT in the interrupt service routine is used for this purpose.
The state of any given channel's interrupt request is directly affected by writes to this register; it is also
affected by writes to the EDMA_CINT. On writes to the EDMA_INT, a 1 in any bit position clears the
corresponding channel's interrupt request. A zero in any bit position has no affect on the corresponding
channel's current interrupt status. The EDMA_CINT is provided so the interrupt request for a single
channel can easily be cleared without the need to perform a read-modify-write sequence to the
EDMA_INT.
Address: 0xFC04_4026 (EDMA_INT)
15 14 13
R INT15 INT14 INT13 INT12 INT11 INT10 INT9
W w1c w1c w1c
Reset 0 0 0
Figure 19-15. eDMA Interrupt Request Register (EDMA_INT)
Field
15–0 eDMA interrupt request n
INTn 0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.
19.4.14 eDMA Error Register (EDMA_ERR)
The EDMA_ERR provide a bit map for the 16 channels, signaling the presence of an error for each
channel. The eDMA engine signals the occurrence of a error condition by setting the appropriate bit in this
register. The outputs of this register are enabled by the contents of the EDMA_EEI,and then routed to the
interrupt controller. During the execution of the interrupt-service routine associated with any DMA errors,
it is software's responsibility to clear the appropriate bit, negating the error-interrupt request. Typically, a
write to the EDMA_CERR in the interrupt-service routine is used for this purpose. The normal DMA
channel completion indicators (setting the transfer control descriptor DONE flag and the possible assertion
of an interrupt request) are not affected when an error is detected.
The contents of this register can also be polled because a non-zero value indicates the presence of a channel
error regardless of the state of the EDMA_EEI. The state of any given channel's error indicators is affected
by writes to this register; it is also affected by writes to the EDMA_CERR. On writes to the EDMA_ERR,
a one in any bit position clears the corresponding channel's error status. A zero in any bit position has no
affect on the corresponding channel's current error status. The EDMA_CERR is provided so the error
indicator for a single channel can easily be cleared.
Freescale Semiconductor
12 11 10 9
INT8
w1c w1c w1c w1c
0 0 0 0
Table 19-16. EDMA_INT Field Descriptions
Enhanced Direct Memory Access (eDMA)
8 7 6 5
INT7 INT6 INT5 INT4
w1c w1c w1c w1c
0 0 0 0
Description
Access: User read/write
4 3 2 1
INT3 INT2 INT1
w1c w1c w1c w1c
0 0 0 0
0
INT0
w1c
0
19-15