Freescale Semiconductor MCF54455 Reference Manual page 480

The FlexBus can support 2-1-1-1 burst cycles to maximize system performance. Delaying termination of
the cycle can add wait states. If internal termination is used, different wait state counters can be used for
the first access and the following beats.
The CSCRn registers enable bursting for reads, writes, or both. Memory spaces can be declared
burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW] bits.
Figure 20-25 shows a longword read to an 8-bit device programmed for burst enable. The transfer results
in a 4-beat burst and the data is driven on
throughout the bus cycle.
In non-multiplexed address/data mode, the address on FB_A increments
only during internally-terminated burst cycles. The first address is driven
throughout the entire burst for externally-terminated cycles.
In multiplexed address/data mode, the address is driven on FB_AD only
during the first cycle for internally- and externally-terminated cycles.
FB_CLK
FB_AD[23:0]
Mux'd Bus
FB_AD[31:24]
FB_A[23:0]
Non-Mux'd Bus
FB_D[31:24]
FB_R/W
FB_ALE
FB_CSn, FB_OE
FB_BE/BWEn, FB_TBST
FB_TSIZ[1:0]
Figure 20-25. Longword-Read Burst from 8-Bit Port 2-1-1-1 (No Wait States)
Figure 20-26 shows a longword write to an 8-bit device with burst enabled. The transfer results in a 4-beat
burst and the data is driven on
bus cycle.
The first beat of any write burst cycle has at least one wait state. If the bus
cycle is programmed for zero wait states (CSCRn[WS] = 0), one wait state
is added. Otherwise, the programmed number of wait states are used.
Freescale Semiconductor
FB_AD[31:24].
S0 S1
ADDR[23:0]
ADDR[31:24]
DATA
ADDR[23:0]
ADDR[31:24]
DATA
FB_TA
FB_AD[31:24].
The transfer size is driven at longword (00) throughout the
The transfer size is driven at longword (00)
NOTE
S2 S2 S2
DATA DATA
ADDR + 1 ADDR + 2
DATA DATA
00
NOTE
S2 S3 S0
DATA
ADDR + 3
DATA
FlexBus
20-27