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Cache
6.3.2
Access Control Registers (ACRn)
The ACRn registers assign control attributes, such as cache mode and write protection, to specified
memory regions. ACR0 and ACR1 control data attributes; ACR2 and ACR3 control instruction attributes.
Registers are accessed with the MOVEC instruction with the Rc encodings in
For overlapping regions, the lower ACR number takes priority. Data transfers to and from these registers
are longword transfers.
ACR0–3 are read/write by the debug module.
BDM: 0x004 (ACR0)
0x005 (ACR1)
0x006 (ACR2)
0x007 (ACR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
R
BA
W
Reset – – – – – – – – – – – – – – – – 0 – – 0 0
1
Reserved in ACR2 and ACR3
I
Field
31–24
Base address. Compared with address bits A[31:24]. Eligible addresses that match are assigned the access
BA
control attributes.
23–16
Address mask. Setting a mask bit causes the corresponding address base bit to be ignored. The low-order mask
ADMSK
bits can be set to define contiguous regions larger than 16 Mbytes. The mask can define multiple non-contiguous
regions of memory.
15
Enable. Enables or disables the other ACRn bits.
E
0 Access control attributes disabled
1 Access control attributes enabled
14–13
Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this address range or if the
S
type of access is a don't care.
00 Match addresses only in user mode
01 Match addresses only in supervisor mode
1x Execute cache matching on all accesses
12–11
Reserved, must be cleared.
10
Address mask mode.
AMM
0 The ACR hit function allows control of a 16 Mbytes or greater memory region.
1 The upper 8 bits of the address and ACR are compared without a mask function. Address bits [23:20] of the
address and ACR are compared using ACR[19:16] as a mask, allowing control of a 1–16 Mbyte memory
region.
9–7
Reserved, must be cleared.
6-8
NOTE
ADMSK
Figure 6-5. Access Control Register Format (ACRn)
Table 6-4. ACRn Field Descriptions
10
9
0 0
0 0 0
E
S
AMM
0
0 0 0 – – 0
Description
Figure
6-5.
Access: MOVEC write-only
Debug read/write
8
7
6
5
4
3
2
1
0
0
0 0
1
CM
W
SP
0
–
0 0
Freescale Semiconductor
0
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