Freescale Semiconductor MCF54455 Reference Manual page 537

PCI Bus Controller
Field
31–28 Reserved, must be cleared.
27–24 Window 0 control. The W0C, as well as the W1C and W2C bit fields contain the following bit structure.
W0C
IO/M#:
0 Window maps to PCI memory.
1 Window maps to PCI I/O.
PCI read command (PRC). If the corresponding IO/M# bit is cleared, these bits determine the type of PCI memory
command to issue. If IO/M# is set, the value of these bits is ignored.
00 PCI
MEMORY READ
01 PCI
MEMORY READ LINE
10 PCI
MEMORY READ MULTIPLE
11 Reserved.
Enable. Indicates the address registers controlling the internal bus initiator interface access to PCI for this window
are initialized and used. The PCI controller can begin to decode internal bus PCI accesses.
0 Do not decode internal bus PCI accesses to window.
1 Registers initialized—decode accesses to window.
23–20 Reserved, must be cleared.
19–16 Window 1 control. See W0C bit for field description.
W1C
15–12 Reserved, must be cleared.
11–8 Window 2 control. See W0C bit for field description.
W2C
7–0 Reserved, must be cleared.
22.3.2.7 Initiator Control Register (PCIICR)
Address: 0xFC0A_8084 (PCIICR)
31 30 29 28 27 26
R 0 0 0 0 0
REE IAE TAE
W
Reset 0 0 0 0 0
22-20
Table 22-16. PCIIWCR Field Descriptions
R
IO/M#
W
Reset
Figure 22-21. Window n Control Bit Fields (WnC)
.
.
.
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Figure 22-22. PCIICR Register
Description
3 2 1
PRC ENABLE
0 0 0
0
0
Access: User read/write
9 8 7 6 5 4 3 2
Maximum Retries
Freescale Semiconductor
1 0