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SDRAM Controller (SDRAMC)
21.4.5
SDRAM Chip Select Configuration Registers (SDCSn)
These registers define base address and space size of each chip select.
Because the SDRAM module is one of the slaves connected to the crossbar
switch, it is only accessible within a certain memory range. The only
applicable address ranges for which the chip-selects can be active are
0x4000_0000 – 0x7FFF_FFFF. Be sure to set the SDCSn registers
appropriately.
The user should not probe memory on a DDR chip select to determine if
memory is connected. If a read is attempted from a DDR SDRAM chip
select when there is no memory to respond with the appropriate DQS pulses,
the bus cycle hangs. Because no high level bus monitor exists on the device,
a reset is the only way to exit the error condition.
Address: 0xFC0B_8110 (SDCS0)
0xFC0B_8114 (SDCS1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-8. SRAM Chip Select Configuration Register (SDCSn)
Field
31–20
Chip-select base address. Because the SDRAM module is one of the slaves connected to the crossbar switch, it is
CSBA
only accessible within a certain memory range. The only applicable address ranges for which the chip-selects can
be active are 0x4000_0000 – 0x7FFF_FFFF. Therefore, the possible range for this field is 0x400 – 0x7FF.
21-16
NOTE
NOTE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CSBA
Table 21-9. SDCSn Field Descriptions
Description
Access: User read/write
8
7
6
5
4
3
2
1
0
CSSZ
Freescale Semiconductor
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