Freescale Semiconductor MCF54455 Reference Manual page 759

DMA Serial Peripheral Interface (DSPI)
The DSPI_MCR[MDIS] bit is set at reset.
Address: 0xFC05_C000 (DSPI_MCR)
31 30 29
R
MSTR DCONF
W
Reset 0 0 0
15 14 13
R 0
DIS_
MDIS
W
TXF
Reset 0 1 0
Figure 31-2. DSPI Module Configuration Register (DSPI_MCR)
Field
31 Master/slave mode select. Configures the DSPI for master mode or slave mode.
MSTR Note: This bit's value must only be changed when the DSPI_MCR[HALT] bit is set. Otherwise, improper operation
may occur.
0 Slave mode
1 Master mode
30 Continuous SCK enable. Enables the serial communication clock (DSPI_SCK) to run continuously. See
CONT_ Section 31.4.5, "Continuous Serial Communications
SCKE 0 Continuous SCK disabled
1 Continuous SCK enabled
29–28 DSPI configuration. Selects between the different configurations of the DSPI.
DCONF 00 SPI
01 Reserved
10 Reserved
11 Reserved
Note: All values except 00 are reserved. This field must be configured for SPI mode for the DSPI module to operate
correctly.
27 Freeze. Enables the DSPI transfers to be stopped on the next frame boundary when the device enters debug mode.
FRZ 0 Do not halt serial transfers
1 Halt serial transfers
26 Modified timing format enable. Enables a modified transfer format to be used. See
MTFE Transfer Format (MTFE = 1, CPHA =
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled
31-6
NOTE
28 27 26 25
PCS
FRZ MTFE
SE
0 0 0 0
12 11 10 9
0 0
DIS_
SMPL_PT
CLR_ CLR_
RXF
TXF RXF
0 0 0 0
Table 31-3. DSPI_MCR Field Descriptions
1)," for more information.
24 23 22 21
RO PCS PCS PCS
OE IS7 IS6 IS5
0 0 0 0
8 7 6 5
0 0 0
0 0 0 0
Description
Clock," for details.
Access: User read/write
20 19 18 17
PCS PCS PCS PCS
IS4 IS3 IS2 IS1
0 0 0 0
4 3 2 1
0 0 0 0
0 0 0 0
Section 31.4.4.4, "Modified SPI
Freescale Semiconductor
16
PCS
IS0
0
0
HALT
1