Dma Serial Peripheral Interface (Dspi) Signals; Synchronous Serial Interface (Ssi) Signals - Freescale Semiconductor MCF54455 Reference Manual

2.3.13

DMA Serial Peripheral Interface (DSPI) Signals

Table 2-15. DMA Serial Peripheral Interface (DSPI) Signals
Signal Name
DSPI Synchronous
Serial Output
DSPI Synchronous
Serial Data Input
DSPI Serial Clock
DSPI Peripheral Chip
Select 5/Peripheral Chip
Select Strobe
DSPI Peripheral Chip
Selects
DSPI Peripheral Chip
Select 0/Slave Select
2.3.14

Synchronous Serial Interface (SSI) Signals

Signal Name
Serial Bit Clock
Serial Master Clock
Serial Frame Sync
Serial Receive Data
Serial Transmit Data
Freescale Semiconductor
Abbreviation
DSPI_SOUT Provides the serial data from the DSPI and can be programmed to be
driven on the rising or falling edge of DSPI_SCK. Each byte is sent
msb first.
DSPI_SIN Provides the serial data to the DSPI and can be programmed to be
sampled on the rising or falling edge of DSPI_SCK. Each byte is
written to RAM lsb first.
DSPI_SCK Provides the serial clock from the DSPI. In master mode, the
processor generates DSPI_SCK, while in slave mode, DSPI_SCK is
an input from an external bus master.
DSPI_PCS5/ When in master mode and the DSPI_MCR[PCSSE] bit cleared,
DSPI_PCSS DSPI_PCS5 is a peripheral chip select output that selects which slave
device the current transmission is intended.
DSPI_PCSS provides a strobe signal that can be used with an
external demultiplexer for deglitching of the DSPI_PCSn signals.
When in master mode and the DSPI_MCR[PCSSE] bit is set,
DSPI_PCSS provides the appropriate timing for the decoding of the
DSPI_PCS[3:0] signals, which prevents glitches from occurring.
In slave mode, this signal is not used.
DSPI_PCS[3:1] Provide DSPI peripheral chip selects that can be programmed to be
active high or low.
DSPI_PCS0/ In master mode, DSPI_PCS0 is a peripheral chip select output that
DSPI_SS selects which slave device the current transmission is intended.
In slave mode, the SS signal is a slave select input that allows an SPI
master to select the processor as the target for transmission.
Table 2-16. SSI Module Signals
Abbreviation
SSI_BCLK Used by the receive and transmit blocks. In gated clock mode,
SSI_BCLK is only valid during transmission of data, otherwise it is
pulled to an inactive state.
SSI_MCLK This clock signal is output from the device when it is the master. When
2
in I S master mode, this signal is referred to as the oversampling
clock. The frequency of SSI_MCLK is a multiple of the frame clock.
SSI_FS Used by transmitter/receiver to synchronize the transfer of data. In
gated clock mode, this signal is not used. When configured as an
input, the external device should drive SSI_FS during the rising edge
of SSI_BCLK.
SSI_RXD Receives data into the receive data shift register
SSI_TXD Transmits data from the serial transmit shift register.
Function
Function
Signal Descriptions
I/O
O
I
I/O
O
O
I/O
I/O
I/O
O
I/O
I
O
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