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Figure 30-1
is a block diagram of one of the four identical timer modules.
DMA Timer
Internal Bus Clock
)
(÷1 or ÷16
DTnIN
DTnOUT
Interrupt Request
DMA Request
30.1.2
Features
Each DMA timer module has:
•
Maximum timeout period of 132,272 seconds at 133 MHz (~38 hours)
•
7.5-ns resolution at 133 MHz
•
Programmable sources for the clock input, including external clock
•
Programmable prescaler
•
Input-capture capability with programmable trigger edge on input pin
•
Programmable mode for the output pin on reference compare
•
Free run and restart modes
•
Programmable interrupt or DMA request on input capture or reference-compare
•
Ability to stop the timer from counting when the ColdFire core is halted
Freescale Semiconductor
Internal Bus to/from DMA Timer Registers
DMA Timer
Clock
Generator
clock
31
Capture
Detection
31
DMA Timer Capture Register (DTCRn)
(latches DTCN value when triggered by
7
(indicates capture or when DTCN = DTRRn)
Figure 30-1. DMA Timer Block Diagram
15
DMA Timer Mode Register (DTMRn)
Prescaler
Mode Bits
Divider
DMA Timer Counter Register (DTCNn)
(contains incrementing value)
0
31
DMA Timer Reference Register (DTRRn)
DTnIN)
(reference value for comparison with DTCN)
DMA Timer Event Register (DTERn)
DMA Timers (DTIM0–DTIM3)
0
7
0
DMA Timer Extended Mode
Register (DTXMRn)
0
0
0
30-2
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