Signal Primary Functions - Freescale Semiconductor MCF52277 Reference Manual

Signal Descriptions
Signal Name
VDD_OSC
VDD_PLL
VDD_USB
VDD_RTC
VDD_ADC
VSS
VSS_OSC
VSS_ADC
1
Pull-ups are generally only enabled on pins with their primary function, except as noted.
2
Refers to pin's primary function.
3
Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
4
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.
5
Pull-up when DREQ controls the pin.
6
The 176 LQFP device only supports a 12-bit LCD data bus.
7
DSPI or SBF signal functionality is controlled by RESET. When asserted, these pins are configured for serial boot; when negated, the
pins are configured for DSPI.
8
Pull-up when the serial boot facility (SBF) controls the pin.
9
If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these
pins.
2.3

Signal Primary Functions

2.3.1 Reset Signals
Table 2-3 describes signals used to reset the chip or to indicate a reset.
Signal Name
Reset In
Reset Out
2-6
Table 2-2. MCF5227x Signal Information and Muxing (continued)
GPIO Alternate 1
— —
— —
— —
— —
— —
— —
— —
— —
Table 2-3. Reset Signals
Abbreviation
RESET Primary reset input to the device. Asserting RESET resets the core and
peripherals after four FB_CLK cycles. Asserting RESET also causes
RSTOUT to be asserted.
RSTOUT Reset output is an indicator that the chip is in reset. RSTOUT is
asserted at least 512 internal system bus clock cycles in response to
any internal or external reset. (The exact time depends on how long it
takes for the PLL to lock and/or the serial boot sequence to complete.)
MCF52277 Reference Manual, Rev. 1
Alternate 2
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Function
MCF52274 MCF52277
176 LQFP 196 MAPBGA
— 108
—
104
— 151
— 101
—
91
— 1, 13, 45, 71, 93, F7, F8, G6–G8,
112, 133, 147 H6–H8, J7, J8
—
107
— 92
I/O
I
O
Freescale Semiconductor
G13
H14
B10
J13
L13
H13
L14