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Field
31–16
Base address. Defines the base address for the 64-Kbyte address space mapped to the MMU.
BA
15–1
Reserved, must be cleared.
0
Valid. Indicates when MMUMBAR contents are valid. BA is not used unless V is set.
V
0 MMUBAR contents are not valid.
1 MMUBAR contents are valid.
4.2.3
MMU Control Register (MMUCR)
MMUCR contains the address space mode and virtual mode enable bits. The user must force pipeline
synchronization after writing to this register. Therefore, all writes to this register must be immediately
followed by a NOP instruction.
MMUBAR
0x000 (MMUCR)
Offset:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
31–2
Reserved, must be cleared.
1
Address space mode. Controls how the address space ID is used for TLB hits.
ASM
0 TLB entry ASID values are compared to the ASID register value for user or supervisor mode unless the TLB entry
is marked shared (MMUTR[SG] = 1). The address space ID register value is the effective address space for all
requests, supervisor and user.
1 Address space 0x00 is reserved for supervisor mode, and the effective address space is forced to 0x00 for all
supervisor accesses. The other 255 address spaces are used to tag user processes. The TLB entry ASID values
are compared to the ASID register for user mode unless the TLB entry is marked shared (SG = 1). The TLB entry
ASID value is always compared to 0x00 for supervisor accesses. This allows two levels of sharing. All users, but
not the supervisor, share an entry if SG is set and ASID does not equal 0. All users and the supervisor share an
entry if SG is set and ASID equals 0
0
Virtual mode enable.
EN
0 Virtual mode is disabled
1 Virtual mode is enabled
Freescale Semiconductor
Table 4-3. MMUBAR Field Descriptions
Description
Figure 4-4. MMU Control Register (MMUCR)
Table 4-4. MMUCR Field Descriptions
Description
Memory Management Unit (MMU)
Access: User read/write
9
8
7
6
5
4
3
2
0
0
0
0
1
0
ASM EN
0
0
4-5
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