Core Data Fault Recovery Registers - Freescale Semiconductor MCF54455 Reference Manual

System Control Module (SCM)
• Upon the first time-out, a watchdog timer interrupt is asserted. If this time-out condition is not
serviced before a second time-out occurs, the CWT asserts a system reset. This configuration
supports a more graceful response to watchdog time-outs.
• In addition to these three basic modes of operation, the CWT also supports a windowed mode of
operation. In this mode, the time-out period is divided into four equal segments and the entire
service sequence of the CWT must occur during the last segment (last 25% of the time-out period).
If the timer is serviced anytime (any write to the CWSR register) in the first 75% of the time-out
period, an immediate system reset occurs.
To prevent the core watchdog timer from interrupting or resetting, the CWSR register must be serviced by
performing the following sequence:
1. Write 0x55 to CWSR.
2. Write 0xAA to CWSR.
Both writes must occur in order before the time-out, but any number of instructions can execute between
the two writes. This allows interrupts and exceptions to occur, if necessary, between the two writes.
If the CWT is enabled and has not timed out, any write of a data value other
than 0x55 or 0xAA causes an immediate system reset, regardless of the
value in the CWCR[CWRI] field.
The timer value is constantly compared with the time-out period specified by CWCR[CWT], and any write
to the CWCR register resets the watchdog timer. In addition, a write-once control bit in the CWCR sets
the CWCR to read-only to prevent accidental updates to this control register from changing the desired
system configuration. After this bit, CWCR[RO], is set, a system reset is required to clear it.
For certain values in the CWCR[CWRI] field, the CWT generates an interrupt response to a time-out. For
these configurations, the SCMISR register provides a program visible interrupt request from the watchdog
timer. During the interrupt service routine which handles this interrupt, the source must be explicitly
cleared by writing a 0x01 to the SCMISR.
14.3.3

Core Data Fault Recovery Registers

To aid in recovery from certain types of access errors, the SCM module supports a number of registers that
capture access address, attribute, and data information on bus cycles terminated with an error response.
These registers can then be read during the resulting exception service routine and the appropriate recovery
performed.
The details on the core fault recovery registers are provided in the above sections. It is important to note
these registers are used to capture fault recovery information on any processor-initiated system bus cycle
terminated with an error.
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NOTE
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