Freescale Semiconductor MCF54455 Reference Manual page 704

and transmitted on the SSI_TXD output. Simultaneously, the receive shift register shifts in the received
data available on the SSI_RXD input. At the end of the time slot, this data is transferred to the Rx data
register.
Continuous
SSI_BCLK
SSI_FS
Tx Data
SSI_TXD
SSI_RXD
Rx Data
Figure 27-28 shows a similar case for internal (SSI generates clock) gated clock mode, and
shows a case for external (SSI receives clock) gated clock mode.
A pull-down resistor is required in gated clock mode, because the clock port
is disabled between transmissions.
The Tx data register is loaded with the data to be transmitted. On arrival of the clock, this data transfers to
the transmit shift register and transmits on the SSI_TXD output. Simultaneously, the receive shift register
shifts in the received data available on the SSI_RXD input, and at the end of the time slot, this data
transfers to the Rx data register. In internal gated clock mode, the Tx data line and clock output port are
tri-stated at the end of transmission of the last bit (at the completion of the complete clock cycle). Whereas,
in external gated clock mode, the Tx data line is tri-stated at the last inactive edge of the incoming bit clock
(during the last bit in a data word).
Gated
SSI_BCLK
Tx Data
SSI_TXD
SSI_RXD
Rx Data
Freescale Semiconductor
Figure 27-27. Normal Mode Timing - Continuous Clock
Figure 27-28. Normal Mode Timing - Internal Gated Clock
NOTE
Synchronous Serial Interface (SSI)
Figure 27-29
27-37