Freescale Semiconductor MC9S08PT60 Reference Manual

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MC9S08PT60 Reference Manual

Supports: MC9S08PT60(A) and MC9S08PT32(A)

Document Number: MC9S08PT60RM

Rev 4, 08/2014

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Page 1 MC9S08PT60 Reference Manual Supports: MC9S08PT60(A) and MC9S08PT32(A) Document Number: MC9S08PT60RM Rev 4, 08/2014...
Page 2 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Port H input/output (I/O) pins (PTH7–PTH6, PTH2–PTH0)................51 2.2.14 True open drain pins (PTA3–PTA2)........................51 2.2.15 High current drive pins (PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, PTH1)........52 2.2.16 Peripheral pinouts............................52 Chapter 3 Power management Introduction..................................55 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 4 Random-access memory (RAM)............................ 77 Flash and EEPROM................................77 4.5.1 Overview................................77 4.5.2 Function descriptions............................79 4.5.2.1 Modes of operation........................79 4.5.2.2 Flash and EEPROM memory map....................80 4.5.2.3 Flash and EEPROM initialization after system reset..............80 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 5 Hardware nested interrupt..........................126 5.1.3.1 Interrupt priority level register....................... 127 5.1.3.2 Interrupt priority level comparator set................... 128 5.1.3.3 Interrupt priority mask update and restore mechanism..............128 5.1.3.4 Integration and application of the IPC................... 129 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 6 Bus clock output pin enable..........................139 System interconnection..............................140 6.5.1 ACMP output selection............................ 140 6.5.2 SCI0 TxD modulation............................140 6.5.3 SCI0 RxD capture............................141 6.5.4 SCI0 RxD filter..............................141 6.5.5 RTC capture..............................142 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 7 Universally Unique Identifier Register 8 (SYS_UUID8)................156 Chapter 7 Parallel input/output Introduction..................................157 Port data and data direction.............................159 Internal pullup enable..............................160 Input glitch filter setting..............................160 High current drive................................161 Pin behavior in stop mode...............................161 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 8 Port G Input Enable Register (PORT_PTGIE)....................184 7.7.25 Port H Input Enable Register (PORT_PTHIE)....................185 7.7.26 Port Filter Register 0 (PORT_IOFLT0)......................186 7.7.27 Port Filter Register 1 (PORT_IOFLT1)......................187 7.7.28 Port Filter Register 2 (PORT_IOFLT2)......................188 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 9 FLL bypassed internal low power (FBILP)................... 208 8.2.2.5 FLL bypassed external (FBE)......................209 8.2.2.6 FLL bypassed external low power (FBELP)................. 209 8.2.2.7 Stop (STOP)........................... 210 8.2.3 FLL lock and clock monitor..........................211 8.2.3.1 FLL clock lock..........................211 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 10 System Clock Gating Control 1 Register (SCG_C1)..................223 8.7.2 System Clock Gating Control 2 Register (SCG_C2)..................224 8.7.3 System Clock Gating Control 3 Register (SCG_C3)..................225 8.7.4 System Clock Gating Control 4 Register (SCG_C4)..................226 Chapter 9 Chip configurations Introduction..................................229 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 11 9.9.2 8-Bit Serial Peripheral Interface (8-bit SPI)....................244 9.9.3 16-bit serial peripheral interface (16-bit SPI)....................246 9.9.4 Inter-Integrated Circuit (I2C)...........................248 9.10 Analog.....................................250 9.10.1 Analog-to-digital converter (ADC)........................250 9.10.1.1 ADC channel assignments......................251 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 12 10.3 Addressing Modes................................267 10.3.1 Inherent Addressing Mode (INH)........................268 10.3.2 Relative Addressing Mode (REL)........................268 10.3.3 Immediate Addressing Mode (IMM)....................... 268 10.3.4 Direct Addressing Mode (DIR)........................269 10.3.5 Extended Addressing Mode (EXT)........................269 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 13 Reset Sequence..............................277 10.6.2 Interrupt Sequence............................277 10.7 Instruction Set Summary..............................278 Chapter 11 Keyboard Interrupts (KBI) 11.1 Introduction..................................291 11.1.1 Features................................291 11.1.2 Modes of Operation............................291 11.1.2.1 KBI in Wait mode.......................... 291 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 14 CHn — FTM channel (n) I/O pin........................304 12.2.3 FAULTj — FTM fault input..........................304 12.3 Memory map and register definition..........................305 12.3.1 Module memory map............................305 12.3.2 Register descriptions............................305 12.3.3 Status and Control (FTMx_SC)........................309 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 15 12.3.24 Fault Input Filter Control (FTMx_FLTFILTER).....................333 12.3.25 Fault Input Control (FTMx_FLTCTRL)......................334 12.4 Functional Description..............................335 12.4.1 Clock Source..............................336 12.4.1.1 Counter Clock Source........................336 12.4.2 Prescaler................................337 12.4.3 Counter................................337 12.4.3.1 Up counting............................337 12.4.3.2 Up-down counting..........................340 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 16 12.4.11.8 Summary of PWM synchronization....................369 12.4.12 Deadtime insertion............................371 12.4.12.1 Deadtime insertion corner cases....................372 12.4.13 Output mask..............................373 12.4.14 Fault control..............................374 12.4.14.1 Automatic fault clearing.........................376 12.4.14.2 Manual fault clearing........................377 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 17 Timer overflow interrupt..........................395 12.6.2 Channel (n) interrupt............................395 12.6.3 Fault interrupt..............................395 Chapter 13 8-bit modulo timer (MTIM) 13.1 Introduction..................................397 13.2 Features................................... 397 13.3 Modes of operation................................. 397 13.3.1 MTIM in wait mode............................398 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 18 RTC Modulo Register: High (RTC_MODH)....................409 14.4.4 RTC Modulo Register: Low (RTC_MODL)....................409 14.4.5 RTC Counter Register: High (RTC_CNTH)....................410 14.4.6 RTC Counter Register: Low (RTC_CNTL)....................410 14.5 Functional description..............................411 14.5.1 RTC operation example........................... 412 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 19 Receiver functional description........................431 15.4.3.1 Data sampling technique........................ 432 15.4.3.2 Receiver wake-up operation......................433 15.4.4 Interrupts and status flags..........................434 15.4.5 Baud rate tolerance............................435 15.4.5.1 Slow data tolerance........................436 15.4.5.2 Fast data tolerance..........................437 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 20 SPI status register (SPIx_S)..........................450 16.3.5 SPI data register (SPIx_D)..........................451 16.3.6 SPI match register (SPIx_M)........................... 452 16.4 Functional Description..............................452 16.4.1 General................................452 16.4.2 Master Mode..............................453 16.4.3 Slave Mode..............................454 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 21 16-Bit Serial Peripheral Interface (16-Bit SPI) 17.1 Introduction..................................469 17.1.1 Features................................469 17.1.2 Modes of operation............................470 17.1.3 Block diagrams..............................471 17.1.3.1 SPI system block diagram......................471 17.1.3.2 SPI module block diagram......................471 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 22 SPI clock formats............................. 493 17.4.7 SPI baud rate generation..........................496 17.4.8 Special features..............................496 17.4.8.1 SS Output............................496 17.4.8.2 Bidirectional mode (MOMI or SISO).................... 497 17.4.9 Error conditions..............................498 17.4.9.1 Mode fault error..........................498 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 23 18.3.2 I2C Frequency Divider register (I2C_F)......................511 18.3.3 I2C Control Register 1 (I2C_C1)........................512 18.3.4 I2C Status register (I2C_S)..........................513 18.3.5 I2C Data I/O register (I2C_D)......................... 515 18.3.6 I2C Control Register 2 (I2C_C2)........................516 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 24 Address matching.............................527 18.4.4 System management bus specification......................528 18.4.4.1 Timeouts............................528 18.4.4.2 FAST ACK and NACK......................... 530 18.4.5 Resets................................530 18.4.6 Interrupts................................530 18.4.6.1 Byte transfer interrupt........................531 18.4.6.2 Address detect interrupt......................... 531 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 25 Conversion Result Low Register (ADC_RL)....................546 19.3.7 Compare Value High Register (ADC_CVH)....................547 19.3.8 Compare Value Low Register (ADC_CVL)....................547 19.3.9 Pin Control 1 Register (ADC_APCTL1)......................548 19.3.10 Pin Control 2 Register (ADC_APCTL2)......................549 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 26 19.6 Application information..............................564 19.6.1 External pins and routing..........................564 19.6.1.1 Analog supply pins.........................564 19.6.1.2 Analog reference pins........................564 19.6.1.3 Analog input pins........................... 565 19.6.2 Sources of error..............................566 19.6.2.1 Sampling error..........................566 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 27 20.4 Functional description..............................576 20.5 Setup and operation of ACMP............................577 20.6 Resets....................................578 20.7 Interrupts..................................578 Chapter 21 Touch Sense Input (TSI) 21.1 Introduction..................................579 21.1.1 Features................................579 21.1.2 Modes of operation............................580 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 28 Software and hardware trigger......................... 593 21.4.5 Scan times................................ 594 21.4.6 Clock setting..............................594 21.4.7 Reference voltage.............................594 21.4.8 Current source..............................595 21.4.9 Pin enable................................. 595 21.4.10 End of scan...............................595 21.4.11 Noise detection mode............................596 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 29 CCITT compliant CRC example........................611 Chapter 23 Watchdog (WDOG) 23.1 Introduction..................................613 23.1.1 Features................................613 23.1.2 Block diagram..............................614 23.2 Memory map and register definition..........................615 23.2.1 Watchdog Control and Status Register 1 (WDOG_CS1)................615 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 30 Fast testing of the watchdog..........................627 23.3.7.1 Testing each byte of the counter....................627 23.3.7.2 Entering user mode........................628 Chapter 24 Development support 24.1 Introduction..................................629 24.1.1 Forcing active background..........................629 24.1.2 Features................................629 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 31 25.3 Memory map and registers..............................651 25.3.1 Debug Comparator A High Register (DBG_CAH)..................652 25.3.2 Debug Comparator A Low Register (DBG_CAL)..................653 25.3.3 Debug Comparator B High Register (DBG_CBH)..................654 25.3.4 Debug Comparator B Low Register (DBG_CBL)...................654 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 32 Trigger modes..........................670 25.4.5 FIFO................................. 672 25.4.5.1 Storing data in FIFO........................673 25.4.5.2 Storing with begin-trigger......................673 25.4.5.3 Storing with end-trigger......................... 673 25.4.5.4 Reading data from FIFO........................ 673 25.4.6 Interrupt priority...............................674 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 33 Section number Title Page 25.5 Resets....................................675 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 34 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 35: Device Overview
EEPROM size (bytes) RAM size (bytes) 4,096 4,096 LQFP-64 QFP-64 LQFP-48 LQFP-44 LQFP-32 Table 1-2. Feature availability Pin number 64-pin 48-pin 44-pin 32-pin Bus frequency (MHz) WDOG Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 36: Mcu Block Diagram
MTIM0 MTIM1 SPI0 (8-bit) SPI1 (16-bit) ACMP SCI0 SCI1 SCI2 ADC channels TSI channels KBI pins GPIO 1.2 MCU block diagram The block diagram below shows the structure of the MCUs. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 37 5. The secondary power pair of V and V (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 1-1. MCU block diagram MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 38: System Clock Distribution
ICSFFCLK ICSCLK ( ~8 MHz after reset SCI0 SPI0 KBI0 FLASH SCI1 SPI1 KBI1 SCI2 ICSLCLK CLKOUT BUSREF CLKOE System Control Figure 1-2. System clock distribution diagram The clock system supplies: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 39 The TCLK1 must be limited to 1/4th frequency of the bus clock for synchronization. • TCLK2 — This is an optional external clock source for the FTM2 module. The TCLK2 must be limited to 1/4th frequency of the bus clock for synchronization. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 40 System clock distribution MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 41: Pins And Connections
Chapter 2 Pins and connections 2.1 Device pin assignment MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 42 PTE6 PTB1/KBI0P5/TxD0/ADP5/TSI3 Pins in bold are not available on less pi n-count packages. 1. High source/sink current pins 2. True open drain pins Figure 2-1. MC9S08PT60 64-pin QFP and LQFP package MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 43 PTA7/FTM2FAULT2/ADP3/TSI1 PTB0/KBI0P4/RxD0/ADP4/TSI2 PTE6 PTB1/KBI0P5/TxD0/ADP5/TSI3 Pins in bold are not available on less pi n-count packages. 1. High source/sink current pins 2. True open drain pins Figure 2-2. MC9S08PT60 48-pin LQFP package MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 44 PTA7/FTM2FAULT2/ADP3/TSI1 PTB6/SDA/XTAL PTB0/KBI0P4/RxD0/ADP4/TSI2 PTB1/KBI0P5/TxD0/ADP5/TSI3 Pins in bold are not available on less pi n-count packages. 1. High source/sink current pins 2. True open drain pins Figure 2-3. MC9S08PT60 44-pin LQFP package MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 45: Pin Functions
PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB1/KBI0P5/TxD0/ADP5/TSI3 1. High source/sink current pins 2. True open drain pins Figure 2-4. MC9S08PT60 32-pin LQFP package Pin functions 2.2.1 Power (V and V are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated lower-voltage source to the CPU and to the MCU's other internal circuitry.
Page 46: Analog Power Supply And Reference Pins (Vdda/Vrefh And Vssa/Vrefl)
Figure 2-6. Analog power supply bypassing is the high reference supply for the ADC, and is internally connected to V REFH is the low reference supply for the ADC, and is internally connected to V REFL MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 47: Oscillator (Xtal, Extal)
C1 and C2 (which are usually the same size). As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 48: External Reset Pin (Reset) And Interrupt Pin (Irq)
IRQ interrupt and is also the input for the BIH and BIL instructions. IRQ is asynchronous external interrupt pins. In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See the following figure for example. PTA5/IRQ/TCLK0/RESET 4.7k Figure 2-8. PTA5/IRQ/TCLK0/RESET external RC filter MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 49: Background/Mode Select (Bkgd/Ms)
Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall time on the BKGD pin. PTA5/IRQ/TCLK0/RESET Optional Manual Reset BKGD/MS Figure 2-9. Typical debug circuit MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 50: Port A Input/Output (I/O) Pins (Pta7-Pta0)
PTD7–PTD0 are general-purpose, bidirectional I/O port pins. These port pins also have selectable pullup devices when configured for input mode, the pullup devices are selectable on an individual port bit basis. The pulling devices are disengaged when configured for output mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 51: Port E Input/Output (I/O) Pins (Pte7-Pte0)
PTA3 and PTA2 operate in true open drain mode. NOTE When configuring IIC to use SDA(PTA2) and SCL(PTA3) pins, if an application uses internal pullups instead of external pullups, the internal pullups remain present setting when the MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 52: High Current Drive Pins (Ptb4, Ptb5, Ptd0, Ptd1, Pte0, Pte1, Pth0, Pth1)
KBI1P1 FTM2CH3 MOSI1 — PTD0 KBI1P0 FTM2CH2 SPSCK1 — — — — PTH7 — — — — — — — PTH6 — — — — Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 53 — ADP3 TSI1 PTA6 FTM2FAULT1 — ADP2 TSI0 — — PTE4 — — — — — — — — — — — — — — Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 54 Disable all modules that share a pin before enabling another module. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 55: Power Management
This is the normal operating mode. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE: 0xFFFF after reset. The power supply is fully regulating and all peripherals can be active in run mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 56: Wait Mode
MCU taking the appropriate interrupt vector. The LPO (≈1 kHz) for the real-time counter clock allows a wakeup from stop3 mode with no external components. When RTC_SC2[RTCPS] is clear, the real-time counter clock function is disabled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 57: Lvd Enabled In Stop Mode
The following table shows the low power mode behaviors. Table 3-1. Low power mode behavior Mode Wait Stop3 Full regulation Full regulation Loose regulation Optional on Optional on Standby Standby FLASH Standby Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 58: Low Voltage Detect (Lvd) System
LVD is disabled upon entering the stop modes unless the SPMSC1[LVDSE] bit is set or active BDM enabled (BDCSCR[ENBDM]=1). If SPMSC1[LVDSE] and SPMSC1[LVDE] are both set, the current consumption in stop3 with the LVD enabled will be greater. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 59: Power-On Reset (Por) Operation
SPMSC1[LVWF] will be set and LVW interrupt will occur. There are four user- selectable trip voltages for the LVW upon each LVDV configuration. The trip voltage is selected by SPMSC2[LVWV]. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 60: Bandgap Reference
LVDRE LVDSE LVDE BGBDS BGBE Write LVWACK Reset PMC_SPMSC1 field descriptions Field Description Low-Voltage Warning Flag LVWF The LVWF bit indicates the low-voltage warning status. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 61 Bandgap Buffer Enable BGBE This bit enables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels. Bandgap buffer disabled. Bandgap buffer enabled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 62: System Power Management Status And Control 2 Register (Pmc_Spmsc2)
Middle 1 trip point selected (V LVW2 Middle 2 trip point selected (V LVW3 High trip point selected (V LVW4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 63: Memory Map
The HCS08 core processor can address 64 KB of memory space. The memory map, shown in the following figure, includes: • User flash memory (flash) • MC9S08PT60: 60,864 bytes; 119 pages of 512 bytes each • MC9S08PT32: 32,768 bytes; 64 pages of 512 bytes each • Random-access memory (RAM) •...
Page 64: Reset And Interrupt Vector Assignments
(high/low) 0xFFB0:FFB1 Vnvm 0xFFB2:FFB3 KBI1 Vkbi1 0xFFB4:FFB5 KBI0 Vkbi0 0xFFB6:FFB7 Vtsi 0xFFB8:FFB9 Vrtc 0xFFBA:FFBB Viic 0xFFBC:FFBD SPI1 Vspi1 0xFEBE:FFBF SPI0 Vspi0 0xFFC0:FFC1 SCI2 transmit Vsci2txd Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 65: Register Addresses And Bit Assignments
4.3 Register addresses and bit assignments The register definitions vary in different memory sizes. The register addresses of unused peripherals are reserved. The following table shows the register availability of the devices. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 66 0x3088—0x308F SCI1 0x3090—0x3097 SCI2 0x3098—0x309F SPI0 0x30A0—0x30A9 SPI1 0x30AC—0x30AD 0x30AF—0x30AF Port high drive enable 0x30B0—0x30B7 Port output enable 0x30B8—0x30BF Port input enable 0x30C0—0x30EA FTM2 0x30EC—0x30EF Port filter 0x30F0—0x30F7 Port pullup 0x30F8—0x30FF MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 67 Bit 0 0x0010 ADC_SC1 COCO AIEN ADCO ADCH FEMPT 0x0011 ADC_SC2 ADACT ADTRG ACFE ACFGT FFULL — — ADLSM 0x0012 ADC_SC3 ADLPC ADIV MODE ADICLK Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 68 FTM1_C0SC CHIE ELSB ELSA — — 0x0036 FTM1_C0VH Bit 15 Bit 8 0x0037 FTM1_C0VL Bit 7 Bit 0 0x0038 FTM1_C1SC CHIE ELSB ELSA — — Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 69 — — — — — — 0x301B DBG_FX PPACC — — — — — — Bit 16 0x301C DBG_C DBGEN BRKEN — — — LOOP1 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 70 LOCK — IREFST CLKST — — 0x303D Reserved — — — — — — — — OSCST OSCINI 0x303E ICS_OSCSC OSCEN — OSCOS — RANGE Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 71 RTC_CNTL CNTL 0x3070 I2C_A1 0x3071 I2C_F MULT 0x3072 I2C_C1 IICEN IICIE TXAK RSTA WUEN — 0x3073 I2C_S IAAS BUSY ARBL IICIF RXAK 0x3074 I2C_D DATA Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 72 0x3091 SCI2_BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SCISWA 0x3092 SCI2_C1 LOOPS RSRC WAKE 0x3093 SCI2_C2 TCIE ILIE 0x3094 SCI2_S1 TDRE RDRF IDLE Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 73 PTDOE PTDOE PTDOE 0x30B3 PORT_PTDOE 0x30B4 PORT_PTEOE PTEOE7 PTEOE6 PTEOE5 PTEOE4 PTEOE3 PTEOE2 PTEOE1 PTEOE0 0x30B5 PORT_PTFOE PTFOE7 PTFOE6 PTFOE5 PTFOE4 PTFOE3 PTFOE2 PTFOE1 PTFOE0 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 74 0x30D8 FTM2_CNTINL Bit 7 Bit 0 0x30D9 FTM2_STATUS CH7F CH6F CH5F CH4F CH3F CH2F CH1F CH0F FAULTI CAPTE PWMSY 0x30DA FTM2_MODE FAULTM WPDIS INIT FTMEN Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 75 ID36 ID35 ID34 ID33 ID32 0x30FC SYS_UUID5 ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24 0x30FD SYS_UUID6 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 76 This security key can be disabled completely by programming the NV_FSEC[KEYEN] bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the flash if needed, MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 77: Random-Access Memory (Ram)
The flash module includes a memory controller that executes commands to modify flash memory contents. The user interface to the memory controller consists of the indexed flash common command object (FCCOB) register, which is written to with MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 78 • 64 KB of flash memory composed of one 64 KB flash block divided into 128 sectors of 512 bytes • Automated program and erase algorithm with verification • Fast sector erase and longword program operation MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 79: Function Descriptions
If a flash and EEPROM command is active, that is, FSTAT[CCIF] = 0, when the MCU requests stop mode, the current NVM operation will be completed before the MCU is allowed to enter stop mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 80: Flash And Eeprom Memory Map
Not all flash are available to users because some addresses are overlapped with RAM, EEPROM, and registers. MC9S08PT60 contains a piece of 64 KB flash in which only 60,864 bytes flash are available for users. This flash block is divided into 128 sectors of 512 bytes.
Page 81: Flash And Eeprom Command Operations
3. Execute valid flash and EEPROM commands according to MCU functional mode and MCU security state. The figure below shows a general flowchart of the flash or EEPROM command write sequence. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 82 Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for CCIF Set? Command Completion Check Figure 4-3. Generic flash and EEPROM command write sequence flowchart MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 83 Setting FCLKDIV[FDIV] too high can destroy the flash and EEPROM memory due to overstress. Setting FCLKDIV[FDIV] too low can result in incomplete programming or erasure of the flash and EEPROM memory cells. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 84 CCOB array contains the command code, followed by the parameters for this specific flash command. For details on the FCCOB settings required by each command, see the flash command descriptions in Flash and EEPROM command summary MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 85 Program flash 0x07 Program once 0x08 Erase all block 0x09 Erase flash block 0x0A Erase flash sector 0x0B Unsecure NVM 0x0C Verify backdoor access key Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 86: Flash And Eeprom Interrupts
DFDIF and SFDIF flags in combination with the FERSTAT[DFDIE] and FERSTAT[SFDIE] interrupt enable bits to generate the flash error interrupt request. The logic used for generating the flash module interrupts is shown in the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 87: Protection
0xC000 0xD000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0xE000 Protection Fixed End 0xF000 0xF800 Flash Configuration Field 16 bytes (0xFF70 0xFF7F) 0xFFFF Figure 4-5. Flash protection memory map MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 88 Table 4 Table 5 The flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 89 FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPROT[FPHS] and FPROT[FPLS] bit descriptions for additional restrictions. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 90 Table 4-16. EEPROM protection address range DPS[2:0] Global address range Protected size 0x3100 – 0x311F 32 bytes 0x3100 – 0x313F 64 bytes 0x3100 – 0x315F 96 bytes Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 91: Security
EEPROM memory via the memory controller. If the keys presented in the verify backdoor access key command match the backdoor keys stored in MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 92 A secured MCU can be unsecured by using the following method to erase the flash and EEPROM memory: 1. Reset the MCU. 2. Set FCDIV register as described in Writing the FCLKDIV register. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 93: Flash And Eeprom Commands
FPROT[FPHDIS], and FPROT[FPOEN] bits and the EEPROT[DPOPEN] bit are set prior to launching the command 0x09 Erase flash block Erase a flash or EEPROM block Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 94 Verify that a given number of bytes starting at the address provided are erased. Section 0x11 Program EEPROM Program up to four bytes in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 95: Flash And Eeprom Command Summary
FERSTAT[SFDIF] and FERSTAT[DFDIF] flags will be set. If the FSTAT[ACCERR] or FSTAT[FPVIOL] bits are set, the user must clear these bits before starting any command write sequence. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 96 Table 4-22. Erase verify block command FCCOB requirements CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters 0x02 Global address [23:16] to identify Flash block Global address [15:0] in flash block to be verified MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 97 FSTAT[MGSTAT] bits will be set. Table 4-25. Erase verify flash section command error handling Register Error bit Error condition FSTAT ACCERR Set if CCOBIX[2:0] != 010 at command launch Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 98 Valid phrase index values for the read once command range from 0x0000 to 0x0007. During execution of the read once command, any attempt to read addresses within flash block will return invalid data. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 99 NVM_FSTAT ACCERR Set if command not available in current mode (see Table 4-9) Set if an invalid global address [23:0] is supplied (see Table 4-6) Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 100 Valid phrase index values for the program once command range from 0x0000 to 0x0007. During execution of the program once command, any attempt to read addresses within flash will return invalid data. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 101 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 1. As found in the memory map for NVM MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 102 Upon clearing FSTAT[CCIF] to launch the erase flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased. The FSTAT[CCIF] flag will be set after the erase flash sector operation has completed. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 103 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 1. As found in the memory map for NVM MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 104 ACCERR Set if backdoor key access has not been enabled (KEYEN[1:0] ≠ 10 NVM_FSTAT Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 105 Level description (CCOBIX = 010) 0x0000 Return to normal level 0x0001 User margin-1 level 0x0002 User margin-0 level 1. Read margin to the erased state 2. Read margin to the programmed state MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 106 Error bit Error condition Set if CCOBIX[2:0] ≠ 010 at command launch FSTAT ACCERR Set if command is not available in current mode (see Table 4-9) Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 107 Table 4-48. Program EEPROM command error handling Register Error Bit Error condition Set if CCOBIX[2:0] < 010 at command launch NVM_FSTAT ACCERR Set if CCOBIX[2:0] >101 at command launch Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 108 Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 109: Flash And Eeprom Registers Descriptions
NOTE The FCLKDIV register must not be written while a flash command is executing (NVM_FSTAT[CCIF] = 0) Address: 3020h base + 0h offset = 3020h Read FDIVLD FDIVLCK FDIV Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 110: Flash Security Register (Nvm_Fsec)
The KEYEN[1:0] bits define the enabling of backdoor key access to the flash module. NOTE: 01 is the preferred KEYEN state to disable backdoor key access. Disabled Disabled Enabled Disabled Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 111: Flash Ccob Index Register (Nvm_Fccobix)
The FCNFG register enables the flash command complete interrupt and forces ECC faults on flash array read access from the CPU. Address: 3020h base + 4h offset = 3024h Read CCIE IGNSF FDFD FSFD Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 112: Flash Error Configuration Register (Nvm_Fercnfg)
4.6.5 Flash Error Configuration Register (NVM_FERCNFG) The FERCNFG register enables the flash error interrupts for the FERSTAT flags. Address: 3020h base + 5h offset = 3025h Read DFDIE SFDIE Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 113: Flash Status Register (Nvm_Fstat)
The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 114: Flash Error Status Register (Nvm_Ferstat)
The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation returning invalid data was Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 115: Flash Protection Register (Nvm_Fprot)
FPVIOL bit will be set in the FSTAT register. The block erase of a flash block is not possible if any of the flash sectors contained in the same flash block are protected. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 116: Eeprom Protection Register (Nvm_Eeprot)
The FPLS bits determine the size of the protected/unprotected area in flash memory. The FPLS bits can only be written to while the FPLIDS bit is set. 4.6.9 EEPROM Protection Register (NVM_EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 117 This field is reserved. Reserved This read-only field is reserved and always has the value 0. EEPROM Protection Size These bits determine the size of the protected area in the EEPROM memory. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 118: Flash Common Command Object Register:high (Nvm_Fccobhi)
During the reset sequence, the FOPT register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0xFF7E located in flash memory as indicated by reset condition. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 119 The NV[7:0] bits are available as nonvolatile bits. During the reset sequence, the FOPT register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0xFF7E located in flash memory. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 120 Flash and EEPROM registers descriptions MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 121: Interrupt
ISR itself, which is called nesting of interrupts. Normally, the I bit is restored to 0 when the CCR is restored from the value stacked on MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 122: Interrupt Stack Frame
CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 123: Interrupt Vectors, Sources, And Local Masks
(I bit in the CCR) is 0, the CPU finishes the current instruction, stacks the PCL, PCH, X, A, and CCR CPU registers, sets the I bit, and then fetches the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 124 RDRF 0xFFC8:FFC9 Vsci1rx SCI1 SCI1 receive LBKDIF LBKDIE RXEDGIF RXEDGIE ORIE NEIE 0xFFCA:FFCB Vsci1err SCI1 SCI1 error FEIE PEIE 0xFFCC:FFCD Vsci0tx SCI0 TRDE SCI0 transmit Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 125 WDOG timeout 0xFFFA:FFFB Virq IRQF IRQIE IRQ interrupt 0xFFFC:FFFD Vswi Core SWI Instruction — Software interrupt WDOG WDOGE Watchdog timer System 0xFFFE:FFFF Vreset LVDRE Low-voltage detect control RESET pin RSTPE External pin MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 126: Hardware Nested Interrupt
• Interrupt priority mask can be modified during main flow or interrupt service execution. • Previous interrupt mask level is automatically stored when interrupt vector is fetched (four levels of previous values accommodated) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 127: Interrupt Priority Level Register
The IPC consists of three major functional blocks: • The interrupt priority level registers • The interrupt priority level comparator set • The interrupt mask register update and restore mechanism MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 128: Interrupt Priority Level Comparator Set
IPM. If the last position of IPMPS is written, the PSF flag indicates that the IPMPS is full. If all the values in the IPMPS were read, the PSE flag indicates that the IPMPS is empty. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 129: Integration And Application Of The Ipc
• Before leaving the interrupt service routine, the previous levels must be restored manually by setting PULIPM bit. Watch out for the full (PSF) bit and empty (PSE) bit. 5.2 IRQ The IRQ (external interrupt) module provides a maskable interrupt input. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 130: Features
When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used so that the IRQ, if enabled, can wake the MCU. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 131: Pin Configuration Options
Interrupt pin request register IRQ memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Interrupt Pin Request Status and Control Register (IRQ_SC) 5.3.1/132 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 132: Interrupt Pin Request Status And Control Register (Irq_Sc)
Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 133: Interrupt Priority Control Register
Interrupt Level Setting Registers n (IPC_ILRS6) 5.4.3/135 3057 Interrupt Level Setting Registers n (IPC_ILRS7) 5.4.3/135 3058 Interrupt Level Setting Registers n (IPC_ILRS8) 5.4.3/135 3059 Interrupt Level Setting Registers n (IPC_ILRS9) 5.4.3/135 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 134: Ipc Status And Control Register (Ipc_Sc)
(ILRxx) value that is greater than or equal to the value of IPM will be presented to the CPU. Writes to this field are allowed, but doing this will not push information to the Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 135: Interrupt Priority Mask Pseudo Stack Register (Ipc_Ipmps)
(ILRSn is ILRS0 through ILRS9). Address: 3Eh base + 3012h offset + (1d × i), where i=0d to 9d Read ILRn3 ILRn2 ILRn1 ILRn0 Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 136 Interrupt Level Register for Source n*4+1 ILRn1 This field sets the interrupt level for interrupt source n*4+1. ILRn0 Interrupt Level Register for Source n*4+0 This field sets the interrupt level for interrupt source n*4+0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 137: System Control
(SP) and system control settings. SP is forced to 0x00FF at reset. This device has the following sources for reset: • Power-on reset (POR) • Low-voltage detect (LVD) • Watchdog (WDOG) timer • Illegal opcode detect (ILOP) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 138: System Options
6.4.3 SCI0 pin reassignment After reset, SCI0 module pinouts of RxD and TxD are mapped on PTB0 and PTB1, respectively. SYS_SOPT1[SCI0PS] bit enables to reassign SCI0 pinouts on PTA2 and PTA3. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 139: Spi0 Pin Reassignment
The system bus clock can be outputted on PTH2 when the SYS_SOPT3[CLKOE] bits are set by nonzero. Before mapping on the pinout, the output of bus clock can be pre-divided by 1, 2, 4, 8, 16, 32, 64, or 128 by setting SYS_SOPT3[BUSREF]. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 140: System Interconnection
TXD0 pinout. When this bit is clear, the TXD is directly mapped on the pinout. To enable IR modulation function, both FTM0CH0 and SCI must be active. The FTM0 counter modulo register specifies the period of the PWM, and the FTM0 channel 0 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 141: Sci0 Rxd Capture
SCI0 external RxD0 pin is released to other shared functions regardless of the configuration of SCI0 pin reassignment. When SCI0 RxD capture function is active, the ACMP output is injected to FTM0CH1 as well. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 142: Rtc Capture
SYS_SOPT2[ADHWT] bits. The following table shows the ADC hardware trigger setting. Table 6-1. ADC hardware trigger setting ADHWT ADC hardware trigger RTC overflow MTIM0 overflow FTM2 init trigger with 8-bit programmable delay FTM2 match trigger with 8-bit programmable delay MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 143: System Control Registers
When a debug host forces reset by writing 1 to the SYS_SBDFR[BDFR] bit, none of the status bits in SRS will be set. The reset state of these bits depends on what caused the MCU to reset. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 144 ENBDM = 0 in the BDCSC register. Reset not caused by an illegal opcode. Reset caused by an illegal opcode. Illegal Address ILAD Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 145: System Background Debug Force Reset Register (Sys_Sbdfr)
SYS_SBDFR field descriptions Field Description 7–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Background Debug Force Reset BDFR Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 146: System Device Identification Register: High (Sys_Sdidh)
HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU. Address: 3000h base + 3h offset = 3003h Read Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 147: System Options Register 1 (Sys_Sopt1)
PTA4. This pin defaults to the BKGD/MS function following any MCU reset. PTA4/ACMPO/BKGD/MS as PTA4 or ACMPO function. PTA4/ACMPO/BKGD/MS as BKGD function. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 148: System Options Register 2 (Sys_Sopt2)
Write FTMSYNC Reset SYS_SOPT2 field descriptions Field Description SCI0 TxD Modulation Select TXDME This bit enables the SCI0 TxD output modulated by FTM0 channel 0. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 149 These bits select the ADC hardware trigger source. All trigger sources start ADC conversion on rising edge. RTC overflow as the ADC hardware trigger. MTIM0 overflow as the ADC hardware trigger. FTM2 init trigger with 8-bit programmable delay. FTM2 match trigger with 8-bit programmable delay. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 150: System Options Register 3 (Sys_Sopt3)
Bus divided by 16. Bus divided by 32. Bus divided by 64. Bus divided by 128. 6.6.8 System Options Register 4 (SYS_SOPT4) Address: 3000h base + 7h offset = 3007h Read DELAY Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 151: Illegal Address Register: High (Sys_Illah)
SYS_ILLAH field descriptions Field Description ADDR[15:8] High 8-bit of illegal address NOTE: For ILAD, it reset to the high 8-bit of the illegal address; in other cases, the reset to values are undetermined. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 152: Illegal Address Register: Low (Sys_Illal)
Address: 3000h base + F8h offset = 30F8h Read ID[63:56] Write Reset * Notes: • x = Undefined at reset. SYS_UUID1 field descriptions Field Description ID[63:56] Universally Unique Identifier MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 153: Universally Unique Identifier Register 2 (Sys_Uuid2)
Address: 3000h base + FAh offset = 30FAh Read ID[47:40] Write Reset * Notes: • x = Undefined at reset. SYS_UUID3 field descriptions Field Description ID[47:40] Universally Unique Identifier MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 154: Universally Unique Identifier Register 4 (Sys_Uuid4)
Address: 3000h base + FCh offset = 30FCh Read ID[31:24] Write Reset * Notes: • x = Undefined at reset. SYS_UUID5 field descriptions Field Description ID[31:24] Universally Unique Identifier MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 155: Universally Unique Identifier Register 6 (Sys_Uuid6)
Address: 3000h base + FEh offset = 30FEh Read ID[15:8] Write Reset * Notes: • x = Undefined at reset. SYS_UUID7 field descriptions Field Description ID[15:8] Universally Unique Identifier MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 156: Universally Unique Identifier Register 8 (Sys_Uuid8)
Address: 3000h base + FFh offset = 30FFh Read ID[7:0] Write Reset * Notes: • x = Undefined at reset. SYS_UUID8 field descriptions Field Description ID[7:0] Universally Unique Identifier MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 157: Parallel Input/Output
• internal pullups disabled (PTxPEn = 0). Additionally, the parallel I/O that support high drive capability are disabled (HDRVE = 0x00) after reset. The following three figures show the structures of each I/O pin. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 158 Introduction PTxPEn PTxOEn PTxDn PTxIEn CPU read PTxDn Figure 7-1. Normal I/O structure PTxPEn PTxOEn PTxIEn PTxDn CPU read PTxDn Figure 7-2. SDA(PTA2)/SCL(PTA3) structure MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 159: Port Data And Data Direction
When a peripheral module or system function is in control of a port pin, the data direction register bit still controls what is returned for reads of the port data register, even though the peripheral system has overriding control of the actual pin direction. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 160: Internal Pullup Enable
1~128 LPOCLKs). This configurable glitch filter can take the place of an on board external analog filter, and greatly improve the EMC performance. Setting register PORT_IOFLTn can configure the filter of the whole port, etc. set PORT_IOFLT0[FLTA] will affect all PTAn pins. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 161: High Current Drive
7.7.14/173 30B5 Port F Output Enable Register (PORT_PTFOE) 7.7.15/174 30B6 Port G Output Enable Register (PORT_PTGOE) 7.7.16/175 30B7 Port H Output Enable Register (PORT_PTHOE) 7.7.17/176 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 162: Port A Data Register (Port_Ptad)
For port A pins that are configured as Hi-Z, a read returns uncertainty data. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out of the corresponding MCU pin. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 163: Port B Data Register (Port_Ptbd)
For port C pins that are configured as Hi-Z, a read returns uncertainty data. Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is driven out of the corresponding MCU pin. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 164: Port D Data Register (Port_Ptdd)
For port E pins that are configured as Hi-Z, a read returns uncertainty data. Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is driven out of the corresponding MCU pin. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 165: Port F Data Register (Port_Ptfd)
For port G pins that are configured as inputs, a read returns the logic level on the pin. For port G pins that are configured as outputs, a read returns the last value that was written to this register. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 166: Port H Data Register (Port_Pthd)
This read-only field is reserved and always has the value 0. Port H Data Register Bit 2 PTHD2 Port H Data Register Bit 1 PTHD1 Port H Data Register Bit 0 PTHD0 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 167: Port High Drive Enable Register (Port_Hdrve)
PTD0 is disabled to offer high current drive capability. PTD0 is enable to offer high current drive capability. PTB5 PTB5 This read/write bit enables the high current drive capability of PTB5 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 168: Port A Output Enable Register (Port_Ptaoe)
Output Enabled for port A bit 4. Output Enable for Port A Bit 3 PTAOE3 This read/write bit enables the port A pin as an output. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 169: Port B Output Enable Register (Port_Ptboe)
Output Enabled for port B bit 6. Output Enable for Port B Bit 5 PTBOE5 This read/write bit enables the port B pin as an output. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 170: Port C Output Enable Register (Port_Ptcoe)
Reset PORT_PTCOE field descriptions Field Description Output Enable for Port C Bit 7 PTCOE7 This read/write bit enables the port C pin as an output. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 171 Output Enable for Port C Bit 0 PTCOE0 This read/write bit enables the port C pin as an output. Output Disabled for port C bit 0. Output Enabled for port C bit 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 172: Port D Output Enable Register (Port_Ptdoe)
Output Enabled for port D bit 2. Output Enable for Port D Bit 1 PTDOE1 This read/write bit enables the port D pin as an output. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 173: Port E Output Enable Register (Port_Pteoe)
Output Enabled for port E bit 4. Output Enable for Port E Bit 3 PTEOE3 This read/write bit enables the port E pin as an output. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 174: Port F Output Enable Register (Port_Ptfoe)
Output Enabled for port F bit 6. Output Enable for Port F Bit 5 PTFOE5 This read/write bit enables the port F pin as an output. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 175: Port G Output Enable Register (Port_Ptgoe)
PTGOE0 Write Reset PORT_PTGOE field descriptions Field Description 7–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 176: Port H Output Enable Register (Port_Pthoe)
This read/write bit enables the port H pin as an output. Output Disabled for port H bit 6. Output Enabled for port H bit 6. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 177: Port A Input Enable Register (Port_Ptaie)
Input enabled for port A bit 6. Input Enable for Port A Bit 5 PTAIE5 This read/write bit enables the port A pin as an input. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 178: Port B Input Enable Register (Port_Ptbie)
This read/write bit enables the port B pin as an input. Input disabled for port B bit 7. Input enabled for port B bit 7. Input Enable for Port B Bit 6 PTBIE6 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 179: Port C Input Enable Register (Port_Ptcie)
Input enabled for port B bit 0. 7.7.20 Port C Input Enable Register (PORT_PTCIE) Address: 0h base + 30BAh offset = 30BAh Read PTCIE7 PTCIE6 PTCIE5 PTCIE4 PTCIE3 PTCIE2 PTCIE1 PTCIE0 Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 180 Input Enable for Port C Bit 0 PTCIE0 This read/write bit enables the port C pin as an input. Input disabled for port C bit 0. Input enabled for port C bit 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 181: Port D Input Enable Register (Port_Ptdie)
Input enabled for port D bit 2. Input Enable for Port D Bit 1 PTDIE1 This read/write bit enables the port D pin as an input. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 182: Port E Input Enable Register (Port_Pteie)
Input enabled for port E bit 4. Input Enable for Port E Bit 3 PTEIE3 This read/write bit enables the port E pin as an input. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 183: Port F Input Enable Register (Port_Ptfie)
Input enabled for port F bit 6. Input Enable for Port F Bit 5 PTFIE5 This read/write bit enables the port F pin as an input. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 184: Port G Input Enable Register (Port_Ptgie)
PTGIE0 Write Reset PORT_PTGIE field descriptions Field Description 7–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 185: Port H Input Enable Register (Port_Pthie)
This read/write bit enables the port H pin as an input. Input disabled for port H bit 6. Input enabled for port H bit 6. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 186: Port Filter Register 0 (Port_Ioflt0)
Description 7–6 Filter selection for input from PTD FLTD BUSCLK FLTDIV1 FLTDIV2 FLTDIV3 5–4 Filter selection for input from PTC FLTC BUSCLK FLTDIV1 FLTDIV2 FLTDIV3 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 187: Port Filter Register 1 (Port_Ioflt1)
FLTDIV3 5–4 Filter selection for input from PTG FLTG BUSCLK FLTDIV1 FLTDIV2 FLTDIV3 3–2 Filter selection for input from PTF FLTF BUSCLK FLTDIV1 FLTDIV2 FLTDIV3 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 188: Port Filter Register 2 (Port_Ioflt2)
Filter selection for input from RESET/IRQ No filter. Select FLTDIV1, and will switch to FLTDIV3 in stop mode automatically. Select FLTDIV2, and will switch to FLTDIV3 in stop mode automatically. FLTDIV3 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 189: Port Clock Division Register (Port_Fclkdiv)
Filter Division Set 2 FLTDIV2 Port Filter Division Set 2 BUSCLK/32. BUSCLK/64. BUSCLK/128. BUSCLK/256. BUSCLK/512. BUSCLK/1024. BUSCLK/2048. BUSCLK/4096. FLTDIV1 Filter Division Set 1 Port Filter Division Set 1 BUSCLK/2. BUSCLK/4. BUSCLK/8. BUSCLK/16. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 190: Port A Pullup Enable Register (Port_Ptape)
NOTE: When configuring to use this pin as output high for IIC, the internal pullup device remains active when PTAPE2 is set. It is automatically disabled to save power when output low. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 191: Port B Pullup Enable Register (Port_Ptbpe)
Hi-Z, these bits have no effect. Pullup disabled for port B bit 5. Pullup enabled for port B bit 5. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 192: Port C Pullup Enable Register (Port_Ptcpe)
Address: 0h base + 30F2h offset = 30F2h Read PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 Write Reset PORT_PTCPE field descriptions Field Description Pull Enable for Port C Bit 7 PTCPE7 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 193 This control bit determines if the internal pullup device is enabled for the associated PTC pin. For port C pins that are configured as outputs or Hi-Z, these bits have no effect. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 194: Port D Pullup Enable Register (Port_Ptdpe)
Hi-Z, these bits have no effect. Pullup disabled for port D bit 3. Pullup enabled for port D bit 3. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 195: Port E Pullup Enable Register (Port_Ptepe)
Hi-Z, these bits have no effect. Pullup disabled for port E bit 6. Pullup enabled for port E bit 6. Pull Enable for Port E Bit 5 PTEPE5 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 196: Port F Pullup Enable Register (Port_Ptfpe)
Pullup enabled for port E bit 0. 7.7.35 Port F Pullup Enable Register (PORT_PTFPE) Address: 0h base + 30F5h offset = 30F5h Read PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 197 Hi-Z, these bits have no effect. Pullup disabled for port F bit 1. Pullup enabled for port F bit 1. Pull Enable for Port F Bit 0 PTFPE0 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 198: Port G Pullup Enable Register (Port_Ptgpe)
This control bit determines if the internal pullup device is enabled for the associated PTG pin. For port G pins that are configured as outputs or Hi-Z, these bits have no effect. Pullup disabled for port G bit 0. Pullup enabled for port G bit 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 199: Port H Pullup Enable Register (Port_Pthpe)
This control bit determines if the internal pullup device is enabled for the associated PTH pin. For port H pins that are configured as outputs or Hi-Z, these bits have no effect. Pullup disabled for port H bit 0. Pullup enabled for port H bit 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 200 Port data registers MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 201: Clock Management
The low-power oscillator (LPO) module is an on-chip low-power oscillator providing 1 kHz reference clock to RTC and watchdog (WDOG). The following figures show the block diagram, highlighting the clock modules. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 202 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 8-1. Device block diagram highlighting clock modules and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 203: Internal Clock Source (Ics)
• FLL lock detector and external clock monitor • FLL lock detector with interrupt capability • External reference clock monitor with reset capability 8.2.1 Function description The following figure shows the ICS block diagram. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 204: Bus Frequency Divider
ICSIRCLK, which can be used as an additional clock source. To re-target the ICSIRCLK frequency, write a new value to the ICS_C3[SCTRIM] and ICS_C4[SCFTRIM] bits to trim the period of the internal reference clock: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 205: Fixed Frequency Clock (Icsffclk)
• BDIV=000 (divide by 1), RDIV ≥ 010 • BDIV=001 (divide by 2), RDIV ≥ 011 • BDIV=010 (divide by 4), RDIV ≥ 100 • BDIV=011 (divide by 8), RDIV ≥ 101 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 206: Bdc Clock
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. The following figure shows the seven states of the ICS as a state diagram. The arrows indicate the allowed movements between the states. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 207: Fll Engaged Internal (Fei)
FLL engaged internal (FEI) is the default mode of operation and is entered when all of the following conditions occur: • ICS_C1[CLKS] bits are written to 0b • ICS_C1[IREFS] bit is written to 1b MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 208: Fll Engaged External (Fee)
The FLL clock is controlled by the internal reference clock, and the FLL loop locks the FLL frequency to the 512 times the internal reference frequency. The ICSLCLK will be available for BDC communications, and the internal reference clock is enabled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 209: Fll Bypassed External (Fbe)
8.2.2.6 FLL bypassed external low power (FBELP) The FLL bypassed external low power (FBELP) mode is entered when all of the following conditions occur: • ICS_C1[CLKS] bits are written to 10 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 210: Stop (Stop)
The DCO frequency changes from the pre-stop value to its reset value and the FLL need to re-acquire the lock before the frequency is stable. Timing sensitive operations must wait for the FLL acquisition time, t , before executing. Aquire MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 211: Fll Lock And Clock Monitor
8.3 Initialization / application information This section provides example code to give some basic direction to a user on how to initialize and configure the ICS module. The example software is implemented in C language. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 212: Initializing Fei Mode
(ICS_OSCINIT == 0); /* waiting until oscillator is ready */ ICS_C1 = 0x10; /* external clock reference (31.25kHz) to FLL, RDIV = 2, external prescalar = 128 */ ICS_C2 = 0x20; /* BDIV = 1, prescalar = 2 */ MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 213: Initializing Fbe Mode
(ICS), the real time counter clock module, and other MCU sub-systems. OSCINIT Initialization Oscillator High Gain XTLCLK Oscillator RANGE Low-Powe r OSCOS OSCOUT EXTAL XTAL Figure 8-4. Oscillator module block diagram MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 214: Bypass Mode
ICS_OSCSC[HGO] = 0, the series resistor R is not used. The feedback resistor R must be carefully selected to get best performance. The figure below shows the typical OSC low-gain mode connection. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 215: High-Gain Configuration
OSC high-gain mode connection. EXTAL XTAL Figure 8-7. OSC high-gain mode connection 8.3.5.4 Initializing external oscillator for peripherals The following code segment demonstrates initializing external oscillator. Example: 8.3.5.4.1 External oscillator initialization routine MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 216: Khz Low-Power Oscillator (Lpo)
In stop modes, the bus clock is disabled for all gated peripherals, regardless of the setting in SCG_Cx registers. 8.6 ICS control registers MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 217: Ics Control Register 1 (Ics_C1)
Selects the amount to divide down the FLL reference clock selected by the IREFS bits. Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. RDIV ICS_OSCSC[RANGE]= 0 ICS_OSCSC[RANGE]= 1 1024 Reserved Reserved Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 218: Ics Control Register 2 (Ics_C2)
Encoding 4 - Divides selected clock by 16. Encoding 5 - Divides selected clock by 32. Encoding 6 - Divides selected clock by 64. Encoding 7 - Divides selected clock by 128. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 219: Ics Control Register 3 (Ics_C3)
LOLIE Determines if an interrupt request is made following a loss of lock indication. The LOLIE bit has an effect only when LOLS is set. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 220: Ics Status Register (Ics_S)
IREFS, RDIV[2:0], or, if in FEI or FBI modes, TRIM[7:0] will cause the lock status bit to clear and stay cleared until the FLL has reacquired lock. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 221: Osc Status And Control Register (Ics_Oscsc)
ICS_OSCSC field descriptions Field Description OSC Enable OSCEN The OSCEN bit enables the external clock for use as ICSERCLK. OSC module disabled. OSC module enabled. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 222: System Clock Gating Control Registers
System Clock Gating Control 1 Register (SCG_C1) 8.7.1/223 300D System Clock Gating Control 2 Register (SCG_C2) 8.7.2/224 300E System Clock Gating Control 3 Register (SCG_C3) 8.7.3/225 300F System Clock Gating Control 4 Register (SCG_C4) 8.7.4/226 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 223: System Clock Gating Control 1 Register (Scg_C1)
This bit controls the clock gate to the MTIM1 module. Bus clock to the MTIM1 module is disabled. Bus clock to the MTIM1 module is enabled. MTIM0 Clock Gate Control MTIM0 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 224: System Clock Gating Control 2 Register (Scg_C2)
Bus clock to the DBG module is disabled. Bus clock to the DBG module is enabled. NVM Clock Gate Control This bit controls the clock gate to the NVM module. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 225: System Clock Gating Control 3 Register (Scg_C3)
This read-only field is reserved and always has the value 0. SCI2 Clock Gate Control SCI2 This bit controls the clock gate to the SCI2 module. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 226: System Clock Gating Control 4 Register (Scg_C4)
NOTE User software should disable the peripheral before disabling the clocks to the peripheral. When clocks are re-enabled to a peripheral, the peripheral registers need to be re-initialized by user software. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 227 KBI0 Clock Gate Control KBI0 This bit controls the clock gate to the KBI0 module. Bus clock to the KBI0 module is disabled. Bus clock to the KBI0 module is enabled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 228 System clock gating control registers MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 229: Chip Configurations
The trigger can also provide extended breakpoint capacity. The on-chip ICE system is optimized for the HCS08 8-bit architecture and supports 64 KB of memory space. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 230: System Modules
The low-power oscillator (LPO) module is an on-chip low-power oscillator providing 1 kHz reference clock to RTC and watchdog (WDOG). The following figures show the block diagram, highlighting the clock modules. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 231 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-1. Device block diagram highlighting clock modules and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 232: Memory
Non-volatile memory (NVM) includes: • Flash memory • MC9S08PT60—60,864 bytes: 119 sectors of 512 bytes • MC9S08PT32—32,768 bytes: 64 sectors of 512 bytes • EEPROM memory • MC9S08PT60—256 bytes: 128 sectors of 2 bytes •...
Page 233: Security
The 16-bit code is calculated for 8-bit of data at a time, and provides a simple check for all accessible memory locations in flash and RAM. The following figure shows the device block diagram highlighting the CRC module. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 234 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-2. Device block diagram highlighting CRC module MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 235: Timers
PTC3/FTM2CH3 PTD1/FTM2CH3 FTM2 channel 4 PTB4/FTM2CH4 channel 5 PTB5/FTM2CH5 fault 1 PTA6/FTM2FAULT1 fault 2 PTA7/FTM2FAULT2 alternate clock PTE7/TCLK2 The following figure shows the device block diagram highlighting FTM modules and pins. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 236 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-3. Device block diagram highlighting FTM modules and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 237: Ftm0 Interconnection
A timer overflow interrupt can be enabled to generate periodic interrupts for time-based software events. MTIM modules may also use external clock source. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 238 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-4. Block diagram highlighting the MTIM modules and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 239: Mtim0 As Adc Hardware Trigger
ADC and TSI module. Furthermore, when the trigger is enabled, RTC can toggle external pin function if the counter overflows. The following figure shows the device block diagram highlighting RTC module and pin. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 240 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-5. Device block diagram highlighting RTC module and pin MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 241: Communication Interfaces
Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. The following figure shows the device block diagram highlighting SCI modules and pins. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 242 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-6. Device block diagram highlighting SCI modules and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 243: Sci0 Infrared Functions
FTM0 FTM1 FTM2 FTMx_SC FTM2_CNTH FTMx_CNTL FTMx_MODH FTMx_MODL FTMx_C0SC FTMx_C0VH FTMx_C0VL FTMx_C1SC FTMx_C1VH FTMx_C1VL FTMx_C2SC FTMx_C2VH FTMx_C2VL FTMx_C3SC FTMx_C3VH FTMx_C3VL FTMx_C4SC FTMx_C4VH FTMx_C4VL FTMx_C5SC FTMx_C5VH Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 244: 8-Bit Serial Peripheral Interface (8-Bit Spi)
MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, etc. The following figure shows the device block diagram highlighting 8-bit SPI module and pins. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 245 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-7. Device block diagram highlighting 8-bit SPI module and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 246: 16-Bit Serial Peripheral Interface (16-Bit Spi)
MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, etc. The following figure shows device block diagram highlighting 16-bit SPI module and pins. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 247 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-8. Device block diagram highlighting 16-bit SPI module and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 248: Inter-Integrated Circuit (I2C)
9.9.4 Inter-Integrated Circuit (I2C) This device contains an inter-integrated circuit (I2C) module for communication with other integrated circuits. The following figure shows the device block diagram highlighting I2C module and pins. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 249 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-9. Device block diagram highlighting I2C module and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 250: Analog
ADC for operation within an integrated microcontroller system-on-chip. The ADC channel assignments, alternate clock function, and hardware trigger function are configured as described following sections. The following figure shows device block diagram highlighting ADC module and pins. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 251: Adc Channel Assignments
(pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-10. Device block diagram highlighting ADC module and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 252 AD22 Temperature sensor 10111 AD23 Bandgap 11000 AD24 Reserved 11001 AD25 Reserved 11010 AD26 Reserved 11011 AD27 Reserved 11100 AD28 Reserved 11101 AD29 REFH 11110 AD30 REFL 11111 Module disabled None MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 253: Alternate Clock
V • Convert the temperature sensor channel (AD22) • By using the calculated value of V , convert the digital value of AD22 into a voltage, V TEMP MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 254: Analog Comparator (Acmp)
When using the bandgap reference voltage as the reference voltage to the built-in DAC, the user must enable the bandgap buffer by setting BGBE =1 in SPMSC1. For value of bandgap voltage reference see Bandgap reference. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 255 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-11. Device block diagram highlighting ACMP modules and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 256: Acmp Configuration Information
ACMP module output can be directly ejected to SCI0 RxD. In this mode, SCI0 external RxD pinout does not work. Any external signal tagged to ACMP inputs can be regarded as input pins. Please refer SCI0 RxD filter. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 257: Human-Machine Interfaces Hmi
This device has two KBI modules with up to 16 keyboard interrupt inputs grouped in two KBI modules available depending on packages. The following figure shows the device block diagram with the KBI modules and pins highlighted. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 258 (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-12. Block diagram highlighting KBI modules and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 259: Touch Sense Input (Tsi)
The following figure shows the device block diagram highlighting TSI module and pins. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 260: Tsi Channel Assignments
(pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded in 32-pin packages. Figure 9-13. Device block diagram highlighting TSI module and pins MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 261: Hardware Trigger
The TSI module supports two triggers: a software and a hardware trigger. The hardware trigger is connected to the RTC overflow flag. When the TSI module has the hardware trigger enabled, the module starts measurement immediately if an RTC overflows. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 262 Human-machine interfaces HMI MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 263: Central Processor Unit
• Relative — 8-bit signed offset to branch destination • Immediate — Operand in next object code byte(s) • Direct — Operand in memory at 0x0000–0x00FF • Extended — Operand anywhere in 64-Kbyte address space MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 264: Programmer's Model And Cpu Registers
The A accumulator is a general-purpose 8-bit register. One input operand from the arithmetic logic unit (ALU) is connected to the accumulator, and the ALU results are often stored into the A accumulator after arithmetic and logical operations. The MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 265: Index Register (H:x)
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 family and is seldom used in new HCS08 V6 programs because it affects only the low-order half of the stack pointer. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 266: Program Counter (Pc)
TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt, provided I was set. 0 Interrupts enabled Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 267: Addressing Modes
Effective address computations do not require extra execution cycles. The HCS08 V6 CPU uses the 16 addressing modes described in the following sections. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 268: Inherent Addressing Mode (Inh)
LDA $55 means to load the value from address $0055 into the accumulator. Without the # symbol, the instruction is erroneously interpreted as a direct addressing instruction. Example: #$55 CPHX #$FFFF LDHX #$67 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 269: Direct Addressing Mode (Dir)
In extended addressing, the full 16-bit address of the memory location to be operated on is provided in the instruction. Extended addressing can access any location in the 64 KB memory map. Example: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 270: Indexed Addressing Mode
The table can begin anywhere and can extend as far as the address map allows. The k value would typically be in H:X, and the address of the beginning of the table would be MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 271: Indexed, 8-Bit Offset With Post Increment (Ix1+)
The sum is the effective address of the operand. If interrupts are disabled, this addressing mode allows the stack pointer to be used as a second "index" register. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 272: Sp-Relative, 16-Bit Offset (Sp2)
This addressing mode is used to move an 8-bit constant to any location in the direct page memory. The source data is the byte immediately following the opcode, and the destination is addressed by the second byte following the opcode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 273: Indexed To Direct, Post Increment
CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in stop mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 274: Wait Mode
MCU operation during software development. Active background mode is entered in any of the following ways: • When the BKGD/MS pin is low at the time the MCU exits reset. • When a BACKGROUND command is received through the BKGD pin. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 275: Security Mode
Core. The core receives an external input signal that, when asserted, informs to the core that the MCU is in secure mode. While in secure mode, the core controls the following set of conditions: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 276 Table 10-2. Security conditions for read access Inputs conditions Read control Ram, flash or Security Program or Current CPU instruction Current access Read access EEPROM enabled vector read from secure memory is via BDC allowed access MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 277: Hcs08 V6 Opcodes
(SWI) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. The CPU sequence for an interrupt is: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 278: Instruction Set Summary
↕ ↕ ↕ ↕ ↕ ADC oprx16,SP – 9ED9 ee ff ↕ ↕ ↕ ↕ ↕ ADC oprx8,SP – 9EE9 ↕ ↕ ↕ ↕ ↕ Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 279 BCC rel Branch if Carry Bit Branch if (C) = 0 – – – – – – Clear – – – – – – DIR (b0) Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 280 BIT ,X − − − ↕ ↕ BIT oprx16,SP − − − 9ED5 ee ff ↕ ↕ BIT oprx8,SP − − − 9EE5 ↕ ↕ Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 281 ↕ – – – – – – DIR (b0) – – – – – – DIR (b1) – – – – – – DIR (b2) Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 282 M ← 0x00 CLR oprx8,X – – – M ← 0x00 CLR ,X – – – M ← 0x00 CLR oprx8,SP – – – 9E6F Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 283 DBNZ opr8a,rel − − − − − − dd rr DBNZA rel − − − − − − DBNZX rel − − − − − − Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 284 3) Push (PCL) SP ← (SP) – 0x0001 Jump to Subroutine JSR oprx16,X − − − − − − ee ff Push (PCH) Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 285 ↕ ↕ ↕ LSL oprx8,SP − − 9E68 ↕ ↕ ↕ ↕ LSR opr8a − − ↕ ↕ ↕ LSRA − − ↕ ↕ ↕ Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 286 Register High) onto 0x0001 Stack Push (X); SP ← (SP) – PSHX Push X (Index − − − − − − Register Low) onto 0x0001 Stack Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 287 Pull (PCH) SP ← (SP) + 0x0001, Pull (PCL) SP ← SP + 0x0001, Pull (PCH) Return from − − − − − − Subroutine Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 288 SUB #opr8i − − ↕ ↕ ↕ ↕ SUB opr8a − − ↕ ↕ ↕ ↕ SUB opr16a − − hh ll ↕ ↕ ↕ ↕ Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 289 − − − − − − Low) to Accumulator SP ← (H:X) – 0x0001 Transfer Index − − − − − − Register to SP Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 290 Table 10-3. Instruction Set Summary (continued) Effect on CCR Address N Z C Source Form Operation Description Mode I bit ← 0, Halt CPU WAIT Enable Interrupts Wait − − − − − for Interrupt MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 291: Keyboard Interrupts (Kbi)
• One software-enabled keyboard interrupt • Exit from low-power modes 11.1.2 Modes of Operation This section defines the KBI operation in: • Wait mode • Stop mode • Background debug mode MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 292: Kbi In Stop Modes
The block diagram for the keyboard interrupt module is shown below.. BUSCLK KBACK V DD RESET KBIxP0 KBIPE0 SYNCHRONIZER KBEDG0 STOP BYPASS KEYBOARD STOP INTERRUPT FF KBIx INTERRUPT REQUEST KBIxPn KBMOD KBIPEn KBIE KBEDGn Figure 11-1. KBI block diagram MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 293: External Signals Description
KBIx Pin Enable Register (KBI0_PE) 11.4.2/294 307D KBIx Edge Select Register (KBI0_ES) 11.4.3/295 KBI Status and Control Register (KBI1_SC) 11.4.1/294 307E KBIx Pin Enable Register (KBI1_PE) 11.4.2/294 307F KBIx Edge Select Register (KBI1_ES) 11.4.3/295 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 294: Kbi Status And Control Register (Kbix_Sc)
Keyboard detects edges only. Keyboard detects both edges and levels. 11.4.2 KBIx Pin Enable Register (KBIx_PE) KBIx_PE contains the pin enable control bits. Address: Base address + 3040h offset Read KBIPE Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 295: Kbix Edge Select Register (Kbix_Es)
KBIx_SC[KBMOD] bit. Edge sensitive can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level sensitivity is selected using the KBIx_ES[KBEDGn] bits. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 296: Edge-Only Sensitivity
If an internal pullup resistor is enabled for an enabled KBI pin, the associated I/O port pull select register (see I/O Port chapter) can be used to select an internal pullup resistor. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 297: Kbi Initialization
3. Before using internal pullup resistors, configure the associated bits in PORT_PTxPE. 4. Enable the KBI pins by setting the appropriate KBIx_PE[KBIPEn] bits. 5. Write to KBIx_SC[KBACK] to clear any false interrupts. 6. Set KBIx_SC[KBIE] to enable interrupts. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 298 Functional Description MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 299: Flextimer Module (Ftm)
A small exception to this is when the FlexTimer clock frequency is twice bus clock frequency to provide extra resolution for high speed PWM applications. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 300: Features
• Each channel can be configured for input capture, output compare, or edge-aligned PWM mode • In input capture mode: • The capture can occur on rising edges, falling edges or both edges • An input filter can be selected for some channels MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 301: Modes Of Operation
FTM does not need to produce a real time reference or provide the interrupt sources needed to wake the MCU from wait mode, the power can then be saved by disabling FTM functions before entering wait mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 302: Block Diagram
The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 303 7 C7VH:L output channel 7 COMP Input capture input MS7B:MS7A mode logic ELS7B:ELS7A DECAPEN CH7F channel 7 COMBINE interrupt CH7IE CPWMS Figure 12-1. FTM block diagram MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 304: Signal Description
FAULTM[1:0] and FAULTEN control bits are defined for each pair of channels. Each FAULTj input is activated by its corresponding FAULTjEN bit in the FLTCTRL register. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 305: Memory Map And Register Definition
Status and Control (FTM0_SC) 12.3.3/309 Counter High (FTM0_CNTH) 12.3.4/310 Counter Low (FTM0_CNTL) 12.3.5/311 Modulo High (FTM0_MODH) 12.3.6/311 Modulo Low (FTM0_MODL) 12.3.7/312 Channel Status and Control (FTM0_C0SC) 12.3.8/312 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 306 12.3.23/332 Fault Input Filter Control (FTM0_FLTFILTER) 12.3.24/333 Fault Input Control (FTM0_FLTCTRL) 12.3.25/334 Status and Control (FTM1_SC) 12.3.3/309 Counter High (FTM1_CNTH) 12.3.4/310 Counter Low (FTM1_CNTL) 12.3.5/311 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 307 Channels Polarity (FTM1_POL) 12.3.21/329 Fault Mode Status (FTM1_FMS) 12.3.22/331 Input Capture Filter Control (FTM1_FILTER0) 12.3.23/332 Input Capture Filter Control (FTM1_FILTER1) 12.3.23/332 Fault Input Filter Control (FTM1_FLTFILTER) 12.3.24/333 Fault Input Control (FTM1_FLTCTRL) 12.3.25/334 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 308 Deadtime Insertion Control (FTM2_DEADTIME) 12.3.19/327 30E3 External Trigger (FTM2_EXTTRIG) 12.3.20/328 30E4 Channels Polarity (FTM2_POL) 12.3.21/329 30E5 Fault Mode Status (FTM2_FMS) 12.3.22/331 30E6 Input Capture Filter Control (FTM2_FILTER0) 12.3.23/332 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 309: Status And Control (Ftmx_Sc)
CPWMS is write protected. It can be written only when MODE[WPDIS] = 1. FTM counter operates in up counting mode. FTM counter operates in up-down counting mode. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 310: Counter High (Ftmx_Cnth)
BDM is active. This assures that if you were in the middle of reading a 16-bit register when BDM became active, it reads the appropriate value from the other half of the 16-bit value after returning to normal execution. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 311: Counter Low (Ftmx_Cntl)
BDM is active. Any write to the modulo register bypasses the buffer latches and directly writes to the modulo register while BDM is active. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 312: Modulo Low (Ftmx_Modl)
Table 12-73. Mode, edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration None Pin not used for Input capture Capture on Rising Edge Only Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 313 Table 12-74. Dual edge capture mode — edge polarity selection ELSnB ELSnA Channel Port Enable Detected Edges Disabled No edge Enabled Rising edge Enabled Falling edge Enabled Rising and falling edges MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 314 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 315: Channel Value High (Ftmx_Cnvh)
BDM was not active. Address: Base address + 6h offset + (3d × i), where i=0d to 5d Read VAL_H Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 316: Channel Value Low (Ftmx_Cnvl)
FTM clock, write the new value to the Counter Initial Value registers and then initialize the FTM counter by writing any value to CNT). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 317: Counter Initial Value Low (Ftmx_Cntinl)
If another event occurs between the read and write operations, the write operation has no effect; therefore, CHF remains set indicating an event has occurred. In this case, a CHF interrupt request is not lost due to the clearing sequence for a previous CHF. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 318 No channel event has occurred. A channel event has occurred. Channel 2 Flag CH2F See the register description. No channel event has occurred. A channel event has occurred. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 319: Features Mode Selection (Ftmx_Mode)
Fault control is enabled for all channels, and the selected mode is the manual fault clearing. Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 320: Synchronization (Ftmx_Sync)
This register configures the PWM synchronization. A synchronization event can perform the synchronized update of MOD, CV, and OUTMASK registers with the value of their write buffer and the FTM counter initialization. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 321 Selects external trigger 0 as the PWM synchronization trigger. External trigger 0 occurs when the FTM detects a rising edge in the trigger 0 input signal. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 322: Initial State For Channel Output (Ftmx_Outinit)
FTMx_OUTINIT field descriptions Field Description Channel 7 Output Initialization Value CH7OI Selects the value that is forced into the channel output when the initialization occurs. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 323 The initialization value is 1. Channel 0 Output Initialization Value CH0OI Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. The initialization value is 1. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 324: Output Mask (Ftmx_Outmask)
Channel output is masked. It is forced to its inactive state. Channel 3 Output Mask CH3OM Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate normally). Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 325: Function For Linked Channels (Ftmx_Combinen)
Address: Base address + 1Eh offset + (1d × i), where i=0d to 2d Read FAULTEN SYNCEN DTEN DECAP DECAPEN COMP COMBINE Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 326 This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel (n+1) output is the same as the channel (n) output. The channel (n+1) output is the complement of the channel (n) output. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 327: Deadtime Insertion Control (Ftmx_Deadtime)
• When DTVAL is 2, 2 counts are inserted. This pattern continues up to a possible 63 counts. DTVAL is write protected. It can be written only when MODE[WPDIS] = 1. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 328: External Trigger (Ftmx_Exttrig)
Enables the generation of the channel trigger when the FTM counter is equal to the CV register. The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 329: Channels Polarity (Ftmx_Pol)
This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high. The channel polarity is active low. Channel 6 Polarity POL6 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 330 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high. The channel polarity is active low. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 331: Fault Mode Status (Ftmx_Fms)
FAULTF while there is no existing fault condition at the fault input n. Writing a 1 to FAULTFn has no effect. FAULTFn bit is also cleared when FAULTF bit is cleared. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 332: Input Capture Filter Control (Ftmx_Filtern)
No fault condition was detected in the fault input. A fault condition was detected in the fault input. 12.3.23 Input Capture Filter Control (FTMx_FILTERn) This register selects the filter value for the inputs of channels. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 333: Fault Input Filter Control (Ftmx_Fltfilter)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. FFVAL Fault Input Filter Selects the filter value for the fault inputs. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 334: Fault Input Control (Ftmx_Fltctrl)
Enables the filter for the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input filter is disabled. Fault input filter is enabled. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 335: Functional Description
12.4 Functional Description The following sections describe the FTM features. The notation used in this document to represent the counters and the generation of the signals is shown in the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 336: Clock Source
Refer to chip specific documentation for further information. Due to FTM hardware implementation limitations, the frequency of the fixed frequency clock must not exceed the system clock frequency. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 337: Prescaler
The value of CNTINH:L is loaded into the FTM counter, and the counter increments until the value of MODH:L is reached, at which point the counter is reloaded with CNTINH:L. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 338 Conversely, if (CNTINH[7] = 0 and CNTINH:L ≠ 0x0000), then the initial value of the FTM counter is a positive number, therefore the FTM counting is up and unsigned. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 339 MODH:L is not recommended as this unusual setting may make the FTM operation difficult to comprehend. However, there is no restriction on this configuration, and an example is shown in the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 340: Up-Down Counting
The TOF bit is set when the FTM counter changes from MODH:L to (MODH:L – 1). If (CNTINH:L = 0x0000), the FTM counting is equivalent to TPM up-down counting; that is, up-down and unsigned counting. See the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 341: Free Running Counter
TOF bit Figure 12-192. Example when the FTM counter is a free running The FTM counter is also a free running counter when all of the following apply: • (FTMEN = 1) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 342: Counter Reset
While in BDM, the input capture function works as configured. When a selected edge event occurs, the FTM counter value, which is frozen because of BDM, is captured into the CnVH:L registers and the CHnF bit is set. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 343: Filter For Input Capture Mode
(the counter exceeds the value of the CHnFVAL[3:0] bits), the state change of the input signal is validated. It is then transmitted as a pulse edge to the edge detector. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 344: Output Compare Mode
Figure 12-195. Channel input filter example 12.4.5 Output compare mode The output compare mode is selected when (DECAPEN = 0), (COMBINE = 0), (CPWMS = 0) and (MSnB:MSnA = 0:1). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 345 CNTH:L channel (n) output previous value previous value CHnF bit TOF bit Figure 12-198. Example of the output compare mode when the match sets the channel output MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 346: Edge-Aligned Pwm (Epwm) Mode
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnVH:L registers, the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however, the channel (n) output is not controlled by FTM. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 347 0xFFFF in order to get a 100% duty cycle EPWM signal. Note • EPWM mode is available only with (CNTINH:L = 0x0000). • EPWM mode with (CNTINH:L ≠ 0x0000) is not recommended and its results are not guaranteed. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 348: Center-Aligned Pwm (Cpwm) Mode
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n) match (FTM counter = CnVH:L) when counting down, and it is forced low at the channel (n) match when counting up; see the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 349 The CPWM mode must not be used when the FTM counter is a free running counter. Note • CPWM mode is available only with (CNTINH:L = 0x0000). • CPWM mode with (CNTINH:L ≠ 0x0000) is not recommended and its results are not guaranteed. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 350: Combine Mode
(n) match channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 12-205. Combine mode The following figures illustrate the generation of PWM signals using combine mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 351 C(n)VH:L = CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 12-208. Channel (n) output if (C(n)V = CNTIN) and (CNTIN < C(n+1)V < MOD) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 352 0% duty cycle with ELSnB:ELSnA = X:1 Figure 12-210. Channel (n) output if (C(n)V = CNTIN) and (CNTIN < C(n+1)V < MOD) and (C(n+1)V is almost equal to MOD) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 353 (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 12-212. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (CnV = C(n+1)V) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 354 (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 12-215. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V > C(n+1)V) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 355 CNTINH:L C(n+1)VH:L channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 12-217. Channel (n) output if (C(n+1)V < CNTIN) and (CNTIN < C(n)V < MOD) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 356 C(n)VH:L CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 12-219. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V < MOD) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 357: Asymmetrical Pwm
The channel (n+1) output is the same as the channel (n) output if all of the following apply: • (FTMEN = 1) • (DECAPEN = 0) • (COMBINE = 1) • (CPWMS = 0) • (COMP = 0) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 358: Update Of The Registers With Write Buffers
If (CLKS[1:0] = 0:0), then MODH:L registers are updated when their second byte is written, independent of FTMEN bit. If (CLKS[1:0] ≠ 0:0 and FTMEN = 0), then MODH:L registers are updated according to the CPWMS bit: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 359: Cnvh:l Registers
FTM counter changes from MODH:L to (MODH:L – 0x0001). If (CLKS[1:0] ≠ 0:0 and FTMEN = 1), then CnVH:L registers are updated according to the selected mode: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 360: Pwm Synchronization
If a trigger n event occurs together with a write to set the TRIGn bit, then the synchronization is made, but the TRIGn bit remains set because of the last write. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 361: Software Trigger
Therefore, it is possible a new write to set SWSYNC happens when FTM is clearing the SWSYNC because it is the selected boundary cycle of PWM synchronization that was started previously by the software trigger event. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 362: Boundary Cycle
MODH:L and CnVH:L registers is made in the first boundary cycle that occurs with valid conditions for MODH:L or CnVH:L synchronization, except if (PWMSYNC = 0 and REINIT = 1). The CNTMAX and CNTMIN bits are cleared only by software. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 363: Modh:l Registers Synchronization
If the trigger event was a hardware trigger, then the trigger enable bit (TRIGn) is cleared when the trigger n event is detected. See the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 364 Figure 12-227. MODH:L synchronization when (PWMSYNC = 0), (REINIT = 1), and software trigger was used If the trigger event was a hardware trigger, then the TRIGn bit is cleared. See the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 365: Cnvh:l Registers Synchronization
The synchronization requires both bytes of CnVH:L to have been written, SYNCEN = 1 and either a hardware or software trigger event as per MODH:L registers synchronization. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 366: Outmask Register Synchronization
If the trigger event was a hardware trigger, then the trigger enable bit (TRIGn) is cleared when the trigger n event is detected. See the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 367: Ftm Counter Synchronization
• If REINIT = 1 and PWMSYNC = 0, then this synchronization is made on the next enabled trigger event. If the trigger event was a software trigger, then the SWSYNC bit is cleared. See the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 368 FTM counter is reset and channel outputs are forced to their initial value Figure 12-236. FTM counter synchronization when (REINIT = 1), (PWMSYNC = 1), and a hardware trigger was used MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 369: Summary Of Pwm Synchronization
CnVH:L are updated with their write buffer contents when the enabled hardware or software trigger occurs. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 370 SWSYNC bit is cleared when the counter reaches its minimum value after the enabled software trigger has occurred. TRIGn bit TRIGn bit is cleared when the enabled hardware trigger has occurred. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 371: Deadtime Insertion
(n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) Figure 12-237. Deadtime insertion with ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 372: Deadtime Insertion Corner Cases
Although in most cases the deadtime delay is not comparable to channels (n) and (n+1) duty cycle, the following figures show examples where the deadtime delay is comparable to the duty cycle. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 373: Output Mask
Any write to a CHnOM bit updates the OUTMASK write buffer. The CHnOM bit is updated with the value of its corresponding bit in the OUTMASK write buffer according OUTMASK register synchronization. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 374: Fault Control
Note Output mask is available only in combine mode. 12.4.14 Fault control The fault control is enabled if (FTMEN = 1) and (FAULTM[1:0] ≠ 0:0). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 375 If the fault control and fault input n are enabled and a rising edge at the fault input n signal is detected, then the FAULTFn bit is set. The FAULTF bit is the logic OR of FAULTFn[3:0] bits. See the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 376: Automatic Fault Clearing
If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the disabled channel outputs are enabled when the fault input signal (FAULTIN) returns to zero and a new PWM cycle begins. See the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 377: Manual Fault Clearing
However, it is recommended to verify the value of the fault input signal (value of the FAULTIN bit) before clearing the FAULTF bit to avoid unpredictable results. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 378: Polarity Control
Polarity control is available only in combine mode. 12.4.16 Initialization The initialization forces the CHnOI bit value to the channel (n) output when a one is written to the INIT bit. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 379: Features Priority
The FTM is able to generate multiple triggers in one PWM period. Because each trigger is generated for a specific channel, several channels are required to implement this functionality. This behavior is described in the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 380: Initialization Trigger
0x0C 0x0D 0x0E 0x0F 0x00 0x01 0x02 0x03 0x04 0x05 FTM counter initialization trigger Figure 12-248. Initialization trigger is generated when the FTM counter achieves the value of CNTINH:L MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 381 Figure 12-251. Initialization trigger is generated if (CNTH:L = CNTINH:L) and (CLKS[1:0] = 0:0) and a value different from zero is written to CLKS[1:0] bits The initialization trigger output provides a trigger signal that is used for on-chip modules. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 382: Capture Test Mode
The next reads of CnVH:L registers return the value that was written to FTM counter and the next reads of CNTH:L register return the next value of the FTM counter. The read coherency mechanism of CNTH:L and CnVH:L registers remains enabled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 383: Dual Edge Capture Mode
(n) of a channel pair. The channel (n) filter can be active in this mode when n is the channels 0 or 2. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 384 C(n)VH:L registers must be read first before reading the C(n+1)VH:L registers. C(n)VH:L registers must be read first than C(n+1)VH:L registers. Note • The CH(n)F, CH(n)IE, MS(n)A, ELS(n)B, and ELS(n)A bits are channel (n) bits. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 385: One-Shot Capture Mode
When the CH(n+1)F bit is set, both edges are captured and the captured values are ready for reading in the C(n)VH:L and C(n+1)VH:L registers. The latest captured values are always available in these registers even after the DECAP bit is cleared. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 386: Pulse Width Measurement
ELS(n +1)B:ELS(n+1)A bits. Both DECAP and CH(n+1)F bits indicate when two edges of the pulse were captured and the C(n)VH:L and C(n+1)VH:L registers are ready for reading. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 387 The CH(n+1)F bit is set when the second edge of this pulse is detected, that is, the edge selected by ELS(n+1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of the pulse were captured and the C(n)VH:L and C(n+1)VH:L registers are ready for reading. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 388: Period Measurement
The DECAPEN bit selects the dual edge capture mode, so it keeps set in all operation mode. The DECAP bit is set to MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 389 While the DECAP bit is set the configured measurements are made. The CH(n)F bit is set when the first rising edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 390: Read Coherency Mechanism
Thus, the channel (n) is configured to capture the FTM counter value when there is a rising edge at channel (n) input signal, and channel (n+1) to capture the FTM counter value when there is a falling edge at channel (n) input signal. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 391 C(n)VH:L and C(n+1)VH:L registers can be accessed first; however, the C(n)VH:L registers must be read prior to the C(n+1)VH:L registers in dual edge capture oneshot and continuous modes for the read coherency mechanism to work properly. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 392: Tpm Emulation
If (FTMEN = 0), then a write to the CnSC register resets the write coherency mechanism of CnVH:L registers. If (FTMEN = 1), then a write to the CnSC register does not reset the write coherency mechanism of CnVH:L registers. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 393: Bdm Mode
• The channels are in input capture mode (Input capture mode) • The channels outputs are zero • The channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0b00). See table "Mode, Edge, and Level Selection" MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 394 CNTH or CNTL registers (item 3). In this case, it is recommended to use the initialization (Initialization) to update the channel output to the selected value (item 4). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 395: Ftm Interrupts
12.6.2 Channel (n) interrupt The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1). 12.6.3 Fault interrupt The fault interrupt is generated when (FAULTIE = 1) and (FAULTF = 1). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 396 FTM Interrupts MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 397: 8-Bit Modulo Timer (Mtim)
• Clock source divide by 1, 2, 4, 8, 16, 32, 64, 128, or 256 13.3 Modes of operation This section defines the MTIM's operation in stop, wait, and background debug modes. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 398: Mtim In Wait Mode
CLOCK 8-BIT COUNTER TRST XCLK AND SELECT SOURCE TSTP (MTIM_CNT) DIVIDE BY SELECT TCLK SYNC 8-BIT COMPARATOR CLKS MTIM_ INTERRU 8-BIT MODULO (MTIM_MOD) TOIE Figure 13-1. Modulo timer (MTIM) block diagram MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 399: External Signal Description
MTIM Counter Register (MTIM0_CNT) 13.6.3/402 MTIM Modulo Register (MTIM0_MOD) 13.6.4/402 MTIM Status and Control Register (MTIM1_SC) 13.6.1/400 MTIM Clock Configuration Register (MTIM1_CLK) 13.6.2/401 MTIM Counter Register (MTIM1_CNT) 13.6.3/402 MTIM Modulo Register (MTIM1_MOD) 13.6.4/402 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 400: Mtim Status And Control Register (Mtimx_Sc)
TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting. MTIM counter is active. MTIM counter is stopped. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 401: Mtim Clock Configuration Register (Mtimx_Clk)
Encoding 4. MTIM clock source/16. 0101 Encoding 5. MTIM clock source/32. 0110 Encoding 6. MTIM clock source/64. 0111 Encoding 7. MTIM clock source/128. 1000 Encoding 8. MTIM clock source/256. Others Default to MTIM clock source/256. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 402: Mtim Counter Register (Mtimx_Cnt)
The MTIM consists of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with nine selectable values. The module also contains software-selectable interrupt logic. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 403 This will prevent the second occurrence from being missed. SC[TOF] is also cleared when a 1 is written to SC[TRST] or when any value is written to the MTIM_MOD register. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 404: Mtim Operation Example
0xAA, it overflows to 0x00 and continues counting. The timer overflow flag, SC[TOF], sets when the counter value changes from 0xAA to 0x00. An MTIM overflow interrupt is generated when SC[TOF] is set, if SC[TOIE] = 1. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 405: Real-Time Counter (Rtc)
• Software selectable clock sources for input to prescaler with programmable 16 bit prescaler • XOSC 32.768KHz nominal. • LPO (~1 kHz) • Bus clock 14.2.1 Modes of operation This section defines the RTC operation in Stop, Wait, and Background Debug modes. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 406: Wait Mode
Figure 14-1. Real-time counter (RTC) block diagram 14.3 External signal description RTCO is the output of RTC. After MCU reset, the RTC_SC1[RTCO] is set to high. When the counter overflows, the output is toggled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 407: Register Definition
RTIE This read/write bit enables real-time interrupts. If RTIE is set, then an interrupt is generated when RTIF is set. Reset clears RTIE to 0. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 408: Rtc Status And Control Register 2 (Rtc_Sc2)
Changing the prescaler value clears the prescaler and RTCCNT counters. Reset clears RTCPS to 0000. If RTCLKS = x0, it is 1; if RTCLKS = x1, it is 128. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 409: Rtc Modulo Register: High (Rtc_Modh)
RTC_MODL, together with RTC_MODH, indicates the value of the 16-bit modulo value. Address: 306Ah base + 3h offset = 306Dh Read MODL Write Reset RTC_MODL field descriptions Field Description MODL RTC Modulo Low MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 410: Rtc Counter Register: High (Rtc_Cnth)
14.4.6 RTC Counter Register: Low (RTC_CNTL) RTC_CNTL, together with RTC_CNTH, indicates the read-only value of the current RTC count of the 16-bit counter. Address: 306Ah base + 5h offset = 306Fh Read CNTL Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 411: Functional Description
64 µs 244.1406 µs 1024 ms 1 µs 128 µs 488.28125 µs 2048 ms 2 µs 256 µs 976.5625 µs 100 ms 4 µs 12.5 µs 1.9531 ms 8 µs 125 µs MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 412: Rtc Operation Example
14.5.1 RTC operation example This section shows an example of the RTC operation as the counter reaches a matching value from the modulo register. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 413 RTC_MODH and RTC_MODL registers. The real-time interrupt flag, RTC_SC1[RTIF], sets when the counter value changes from 0x7FFF to 0x0000. The RTC_SC1[RTCO] toggles as well when the RTC_SC1[RTIF] is set. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 414: Initialization/Application Information
/* 60 minutes in an hour */ if (Minutes > 59) Hours++; Minutes = 0; /* 24 hours in a day */ if (Hours > 23) Days ++; Hours = 0; MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 415: Serial Communications Interface (Sci)
• Selectable transmitter output polarity 15.1.2 Modes of operation See Section Functional description for details concerning SCI operation in these modes: • 8- and 9-bit data modes • Stop mode operation MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 416: Block Diagram
TO TxD Transmit Control Pin Logic TxD Direction TXDIR BRK13 TDRE Tx Interrupt Request TCIE Figure 15-1. SCI transmitter block diagram The following figure shows the receiver portion of the SCI. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 417 RDRF IDLE ILIE Rx Interrupt Request LBKDIF LBKDIE From RxD Pin Active Edge RXEDGIF Detect RXEDGIE ORIE FEIE Error Interrupt Request NEIE Parity Checking PEIE Figure 15-2. SCI receiver block diagram MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 418: Sci Signal Descriptions
SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 419: Sci Baud Rate Register: High (Scix_Bdh)
SCI_BDH to buffer the high half of the new value and then write to SCI_BDL. The working value in SCI_BDH does not change until SCI_BDL is written. Address: Base address + 0h offset Read LBKDIE RXEDGIE SBNS Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 420: Sci Baud Rate Register: Low (Scix_Bdl)
These 13 bits in SBR[12:0] are referred to collectively as BR. They set the modulo divide rate for the SCI baud rate generator. When BR is cleared, the SCI baud rate generator is disabled to reduce supply current. When BR is 1 - 8191, the SCI baud rate equals BUSCLK/(16×BR). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 421: Sci Control Register 1 (Scix_C1)
10 or 11 bit times of logic high level needed by the idle line detection logic. Idle character bit count starts after start bit. Idle character bit count starts after stop bit. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 422: Sci Control Register 2 (Scix_C2)
Hardware interrupt requested when RDRF flag is 1. Idle Line Interrupt Enable for IDLE ILIE Hardware interrupts from IDLE disabled; use polling. Hardware interrupt requested when IDLE flag is 1. Transmitter Enable Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 423: Sci Status Register 1 (Scix_S1)
This register has eight read-only status flags. Writes have no effect. Special software sequences, which do not involve writing to this register, clear these status flags. Address: Base address + 4h offset Read TDRE RDRF IDLE Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 424 The advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bits. If any of these samples disagrees with the rest of the samples Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 425: Sci Status Register 2 (Scix_S2)
LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected. LBKDIF is cleared by writing a 1 to it. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 426 This status flag can be used to check whether an SCI character is being received before instructing the MCU to go to stop mode. SCI receiver idle waiting for a start bit. SCI receiver active (RxD input not idle). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 427: Sci Control Register 3 (Scix_C3)
NEIE This bit enables the noise flag (NF) to generate hardware interrupt requests. NF interrupts disabled; use polling). Hardware interrupt requested when NF is set. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 428: Sci Data Register (Scix_D)
Read receive data buffer 2 or write transmit data buffer 2. R2T2 Read receive data buffer 1 or write transmit data buffer 1. R1T1 Read receive data buffer 0 or write transmit data buffer 0. R0T0 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 429: Functional Description
Freescale SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ±4 percent for 9-bit data MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 430: Transmitter Functional Description
Writing 0 to SCI_C2[TE] does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 431 If the receiving device is another Freescale Semiconductor SCI, the break characters are received as 0s in all eight data bits and a framing error (SCI_S1[FE] = 1) occurs.
Page 432: Receiver Functional Description
In the case of the start bit, the bit is assumed to be 0 if at least two of the samples at MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 433: Receiver Wake-Up Operation
SCI_BDH[SBNS] selects 1-bit or 2-bit stop bit number that determines how many bit times of idle are needed to constitute a full character time, 10 or 11 or 12 bit times because of the start and stop bits. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 434: Interrupts And Status Flags
SCI_D. If the transmit interrupt enable (SCI_C2[TIE]) bit is set, a hardware interrupt is requested when SCI_S1[TDRE] is set. Transmit complete (SCI_S1[TC]) indicates that the transmitter is MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 435: Baud Rate Tolerance
This function depends on the receiver being enabled (SCI_C2[RE] = 1). 15.4.5 Baud rate tolerance A transmitting device may operate at a baud rate below or above that of the receiver. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 436: Slow Data Tolerance
RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit or 2 stop bits character with no errors is: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 437: Fast Data Tolerance
11 bit times x 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit or 2 stop bits character with no errors is: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 438: Additional Sci Functions
In custom protocols, the ninth bit can also serve as a software-controlled marker. 15.4.6.2 Stop mode operation During all stop modes, clocks to the SCI module are halted. No SCI module registers are affected in Stop3 mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 439: Loop Mode
In single-wire mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 440 Functional description MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 441: 8-Bit Serial Peripheral Interface (8-Bit Spi)
• Master mode or slave mode operation • Full-duplex or single-wire bidirectional mode • Programmable transmit bit rate • Double-buffered transmit and receive data register • Serial clock phase and polarity options • Slave select output MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 442: Modes Of Operation
16.1.3 Block Diagrams This section includes block diagrams showing SPI system connections, the internal organization of the SPI module, and the SPI clock dividers that control the master mode bit rate. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 443: Spi System Block Diagram
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 444: External Signal Description
SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to other functions that are not controlled by the SPI (based on chip configuration). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 445: Spsck - Spi Serial Clock
SPI is enabled as a master and MODFEN is 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE is 0) or as the slave select output (SSOE is 1). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 446: Register Definition
This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, the SPI is disabled and forced into an idle state, and all status bits in the S register are reset. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 447 This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. SPI serial data transfers start with most significant bit SPI serial data transfers start with least significant bit MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 448: Spi Control Register 2 (Spix_C2)
This bit is used for power conservation while the device is in wait mode. SPI clocks continue to operate in wait mode SPI clocks stop when the MCU enters wait mode Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 449: Spi Baud Rate Register (Spix_Br)
Baud rate prescaler divisor is 4 Baud rate prescaler divisor is 5 Baud rate prescaler divisor is 6 Baud rate prescaler divisor is 7 Baud rate prescaler divisor is 8 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 450: Spi Status Register (Spix_S)
Value in the receive data buffer does not match the value in the SPI_M register Value in the receive data buffer matches the value in the SPI_M register Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 451: Spi Data Register (Spix_D)
There is no indication for a receive overrun condition, so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 452: Spi Match Register (Spix_M)
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While the SPE bit is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SPSCK) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 453: Master Mode
• In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. • SS pin MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 454: Slave Mode
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register • SS pin MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 455 SPRF flag in the SPI Status Register is set. Note A change of the bits BIDIROE with SPC0 set, CPOL, CPHA, SSOE, LSBFE, MODFEN, and SPC0 in slave mode will corrupt a transmission in progress and must be avoided. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 456: Spi Clock Formats
SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 457 2. A new data byte is written to the transmit buffer before the in-progress transmission is complete. 3. When the in-progress transmission is complete, the new, ready data byte is transmitted immediately. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 458 BIT 1 LSB FIRST BIT 0 BIT 1 BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 16-16. SPI Clock Formats (CPHA = 0) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 459: Spi Baud Rate Generation
1, 2, 3, 4, 5, 6, 7, or 8 BIT RATE 256, or 512 SPPR2:SPPR1:SPPR0 SPR3:SPR2:SPR1:SPR0 Figure 16-17. SPI Baud Rate Generation 16.4.6 Special Features The following section shows the module special features. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 460: Bidirectional Mode (Momi Or Siso)
The same pin is also the serial input to the shift register. The SPSCK is an output for the master mode and an input for the slave mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 461: Error Conditions
MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for the SPI system configured in slave mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 462: Low Power Mode Options
SPIx_D to the master, it continues to send the same byte. Otherwise, if the slave is currently sending the last data received byte from the master, it continues to send each previously received data from the master byte). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 463: Spi In Stop Mode
• If a data transmission occurs in slave mode after a reset without a write to SPIx_D, the transmission consists of "garbage" or the data last received from the master before the reset. • Reading from SPIx_D after reset always returns zeros. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 464: Interrupts
SPI Status Register details. If the SPRF is not serviced before the end of the next transfer (that is, SPRF remains active throughout another transfer), the subsequent transfers are ignored and no new data is copied into the Data register. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 465: Sptef
5. In the master, read SPIx_S while SPTEF = 1, and then write to the transmit data register (SPIx_D ) to begin transfer. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 466: Pseudo-Code Example
Flag is set when SPI_M = receive data buffer Bit 5 SPTEF Flag is set when transmit data buffer is empty Bit 4 MODF Mode fault flag for master mode Bit 3:0 Reserved MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 467 SPRF = 1 READ SPIx_D SPMF = 1 READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 16-18. Initialization Flowchart Example for SPI Master Device MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 468 Initialization/Application Information MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 469: Introduction
17.1.1 Features The SPI includes these distinctive features: • Master mode or slave mode operation • Full-duplex or single-wire bidirectional mode • Programmable transmit bit rate MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 470: Modes Of Operation
CPU enters run mode. If the SPI is configured as a slave, reception and transmission of a data continues, so that the slave stays synchronized to the master. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 471: Block Diagrams
SS pin as an optional slave select output. MASTER SLAVE MOSI MOSI SPI SHIFTER SPI SHIFTER MISO MISO 8 OR 16 BITS 8 OR 16 BITS SPSCK SPSCK CLOCK GENERATOR Figure 17-1. SPI system connections MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 472: Spi Module Block Diagram
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 473: External Signal Description
SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to other functions that are not controlled by the SPI (based on chip configuration). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 474: Spsck — Spi Serial Clock
SPI is enabled as a master and MODFEN is 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE is 0) or as the slave select output (SSOE is 1). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 475: Memory Map/Register Definition
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): Enables the interrupt for SPI receive buffer full (SPRF) and mode fault (MODF) events. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 476 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 477: Spi Control Register 2 (Spix_C2)
16-bit SPI shift register, match register, and buffers This field is reserved. Reserved Do not write to this reserved bit. Master Mode-Fault Function Enable MODFEN Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 478: Spi Baud Rate Register (Spix_Br)
Use this register to set the prescaler and bit rate divisor for an SPI master. This register may be read or written at any time. Address: 30A0h base + 2h offset = 30A2h Read SPPR[2:0] SPR[3:0] Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 479: Spi Status Register (Spix_S)
• The RNFULLF and TNEAREF help improve the efficiency of FIFO operation when transfering large amounts of data. These flags provide a "watermark" feature of the FIFOs to allow continuous transmissions of data when running at high speed. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 480 Value in the receive data buffer does not match the value in the MH:ML registers Value in the receive data buffer matches the value in the MH:ML registers Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 481 NOTE: At an initial POR, the values of TNEAREF and RFIFOEF are 0. However, the status (S) register and both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If this Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 482: Spi Data Register High (Spix_Dh)
17.3.5 SPI data register high (SPIx_DH) Refer to the description of the DL register. Address: 30A0h base + 4h offset = 30A4h Read Bits[15:8] Write Reset SPI1_DH field descriptions Field Description Bits[15:8] Data (high byte) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 483: Spi Data Register Low (Spix_Dl)
16-bit value into the transmit data buffer. Address: 30A0h base + 5h offset = 30A5h Read Bits[7:0] Write Reset SPI1_DL field descriptions Field Description Bits[7:0] Data (low byte) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 484: Spi Match Register High (Spix_Mh)
SPI match registers. Address: 30A0h base + 7h offset = 30A7h Read Bits[7:0] Write Reset SPI1_ML field descriptions Field Description Bits[7:0] Hardware compare value (low byte) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 485: Spi Control Register 3 (Spix_C3)
RNFULLF is set when the receive FIFO has 32 bits or more Interrupt clearing mechanism select INTCLR This bit selects the mechanism by which the SPRF, SPTEF, TNEAREF, and RNFULLF interrupts are cleared. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 486: Spi Clear Interrupt Register (Spix_Ci)
FIFO are flushed with the corresponding error flags set. These flags are cleared when the CI register is read while the flags are set. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 487 Receive FIFO full flag clear interrupt SPRFCI Writing 1 to this bit clears the SPRF interrupt provided that C3[3] is set. 17.4 Functional description This section provides the functional description of the module. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 488: General
• The SPR3, SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and determine the speed of the MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 489: Slave Mode
17.4.3 Slave mode The SPI operates in slave mode when the MSTR bit in SPI Control Register 1 is clear. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 490 Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on C1[LSBFE]. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 491: Spi Fifo Mode
IPBus (ips_rdata[7:0]) Read Access SPI_REG_BLOCK spidh:l_rx_reg SPI Data Register FIFO depth = 8 bytes FIFO Ctrlr RX- FIFO SPI_CORE_SHFR Load Control shfr_rx_reg Figure 17-23. SPIH:L read side structural overview in FIFO mode MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 492: Data Transmission Length
SPI system into idle state, and reset all status bits in the SPIx_S register. To initiate a transfer after writing to MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 493: Spi Clock Formats
The SS IN waveform applies to the slave select input of a slave. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 494 2. A new data byte is written to the transmit buffer before the in-progress transmission is complete. 3. When the in-progress transmission is complete, the new, ready data byte is transmitted immediately. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 495 BIT 1 LSB FIRST BIT 0 BIT 1 BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 17-26. SPI clock formats (CPHA = 0) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 496: Spi Baud Rate Generation
1, 2, 3, 4, 5, 6, 7, or 8 BIT RATE 256, or 512 SPPR2:SPPR1:SPPR0 SPR3:SPR2:SPR1:SPR0 Figure 17-27. SPI baud rate generation 17.4.8 Special features The following section describes the special features of SPI module. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 497: Bidirectional Mode (Momi Or Siso)
The same pin is also the serial input to the shift register. The SPSCK is an output for the master mode and an input for the slave mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 498: Error Conditions
MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for the SPI system configured in slave mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 499: Low-Power Mode Options
Otherwise, if the slave is currently sending the last data received byte from the master, it continues to send each previously received data from the master byte). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 500: Spi In Stop Mode
• If a data transmission occurs in slave mode after a reset without a write to SPIx_DH:SPIx_DL, the transmission consists of "garbage" or the data last received from the master before the reset. • Reading from SPIx_DH:SPIx_DL after reset always returns zeros. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 501: Interrupts
In 8-bit mode, SPRF is set only after all 8 bits have been shifted out of the shift register and into SPIx_DL. In 16-bit mode, SPRF is set only after all 16 bits have been shifted out of the shift register and into SPIx_DH:SPIx_DL. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 502: Sptef
Clearing this interrupt depends on the state of C3[3] and the status of TNEAREF. Refer to the description of the SPI status (S) register. 17.4.12.6 RNFULLF The RNFULLF bit applies when the FIFO feature is supported. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 503: Initialization/Application Information
2. Clock phase and polarity are set for an active-high SPI clock where the first edge on SPSCK occurs at the start of the first cycle of a data transfer. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 504 In 16-bit mode, this register holds bits 8–15 of the hardware match buffer. In 8-bit mode, writes to this register will be ignored. SPIx_ML = 0xXX Holds bits 0–7 of the hardware match buffer. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 505 SPMF = 1 READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 17-28. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for FIFOMODE = 0 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 506 TXFULLF = 1 RNFULLF = 1/ SPRF = 1 READ SPIxDH:SPIxDL RFIFOEF = 1 CONTINUE Figure 17-29. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for FIFOMODE = 1 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 507: Introduction
• Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation and detection • Repeated START signal generation and detection • Acknowledge bit generation and detection MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 508: Modes Of Operation
Stop3 mode. The STOP instruction does not affect the I2C module's register states. 18.1.3 Block diagram The following figure is a functional block diagram of the I2C module. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 509: Signal Descriptions
C are shown in the table found here. Table 18-1. I C signal descriptions Signal Description Bidirectional serial clock line of the I C system. Bidirectional serial data line of the I C system. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 510: Memory Map/Register Definition
7-bit address scheme and the lower seven bits in the 10-bit address scheme. This field is reserved. Reserved This read-only field is reserved and always has the value 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 511: I2C Frequency Divider Register (I2C_F)
C baud rate of 100 kbit/s. Hold times (μs) MULT SCL Start SCL Stop 3.500 3.000 5.500 2.500 4.000 5.250 2.250 4.000 5.250 2.125 4.250 5.125 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 512: I2C Control Register 1 (I2C_C1)
Therefore, for address cycles, this bit is always set. When addressed as a slave this bit must be set by software according to the SRW bit in the status register. Receive Transmit Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 513: I2C Status Register (I2C_S)
I2C data register in transmit mode. Transfer in progress Transfer complete Addressed As A Slave IAAS This bit is set by one of the following conditions: Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 514 0 or 1 to TXAK after this bit is set in receive mode. • One byte transfer, excluding ACK/NACK bit, completes if FACK is 1. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 515: I2C Data I/O Register (I2C_D)
RSTA (repeated start bit) is used for the address transfer and must consist of the calling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 516: I2C Control Register 2 (I2C_C2)
Contains the upper three bits of the slave address in the 10-bit address scheme. This field is valid only while the ADEXT bit is set. 18.3.7 I2C Programmable Input Glitch Filter Register (I2C_FLT) Address: 3070h base + 6h offset = 3076h Read Reserved Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 517: I2C Range Address Register (I2C_Ra)
However, the SHTF1 bit is set to 1 in the bus transmission process with the idle bus state. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 518 (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it. NOTE: The low timeout function is disabled when the SLT register's value is 0. No low timeout occurs Low timeout occurs Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 519: I2C Address Register 2 (I2C_A2)
This read-only field is reserved and always has the value 0. 18.3.11 I2C SCL Low Timeout Register High (I2C_SLTH) Address: 3070h base + Ah offset = 307Ah Read SSLT[15:8] Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 520: I2C Scl Low Timeout Register Low (I2C_Sltl)
The value of these resistors depends on the system. Normally, a standard instance of communication is composed of four parts: 1. START signal 2. Slave address transmission 3. Data transfer 4. STOP signal MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 521: Start Signal
The R/W bit tells the slave the desired direction of data transfer. • 1 = Read transfer: The slave transmits data to the master • 0 = Write transfer: The master transmits data to the slave MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 522: Data Transfers
18.4.1.4 STOP signal The master can terminate the communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of SDA while SCL is asserted. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 523: Repeated Start Signal
Afterward there is no difference between the device clocks and the state of SCL, and all devices start counting their high periods. The first device to complete its high period pulls SCL low again. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 524: Handshaking
±2 or ±4 when ICR's value ranges from 00h to 0Fh. These potentially varying SCL divider values are highlighted in the following table. For the actual SCL divider values for your device, see the chip-specific details about the I2C module. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 525 (stop) (hex) (hex) value value (clocks) value value 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 526: Bit Address
A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 527: Address Matching
When the I2C module responds to one of these addresses, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the Data register after the first byte transfer to determine that the address is matched. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 528: System Management Bus Specification
When the I2C module is a slave, if it detects the condition, it resets its communication and is then able to receive a new TIMEOUT,MIN START condition. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 529 START to the STOP. When CSMBCLK LOW:SEXT TIMEOUT SEXT occurs, SEXT rises and also triggers SLTF. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 530: Fast Ack And Nack
NACK to the bus, so FACK must be switched off before the last byte transmits. 18.4.5 Resets The I2C module is disabled after a reset. The I2C module cannot cause a core reset. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 531: Interrupts
GCAEN bit is set and a general call is received, the IAAS bit in the Status Register is set. The CPU is interrupted, provided the IICIE bit is set. The CPU must check the SRW bit and set its Tx mode accordingly. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 532: Exit From Low-Power/Stop Modes
The SHTF2's timeout period is the same as that of SHTF1, which is short compared to that of SLTF, so another control bit, SHTF2IE, is added to enable or disable it. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 533: Programmable Input Glitch Filter
To avoid I2C transfer problems resulting from the situation, firmware should prevent the MCU execution of a STOP instruction when the I2C module is in the middle of a transfer. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 534: Initialization/Application Information
Data register. An example of an I2C driver which implements many of the steps described here is available in AN4342: Using the Inter-Integrated Circuit on ColdFire+ and Kinetis MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 535 2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address. Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer. Figure 18-18. Typical I2C interrupt routine MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 536 (in worst case) of the 9th SCL cycle. 3. This read is a dummy read in order to reset the SMBus receiver state machine. Figure 18-19. Typical I2C SMBus interrupt routine MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 537: Introduction
• Operation in Wait or Stop3 modes for lower noise operation • Asynchronous clock source for lower noise operation • Selectable asynchronous hardware conversion trigger • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 538: Block Diagram
ASYNC CLOCK GENERATOR ADICLK ADIV Figure 19-1. ADC Block Diagram 19.2 External Signal Description The ADC module supports up to 24 separate analog inputs. It also requires four supply/ reference/ground connections. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 539 In some packages, V REFL REFL connected internally to V . If externally available, connect the V pin to the same REFL voltage potential as V MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 540: Analog Channel Inputs (Adx)
ADC_SC4[AFDEP]. Any write 0x1F to these bits will reset the FIFO and stop the conversion if it is active. Address: 10h base + 0h offset = 10h Read COCO AIEN ADCO ADCH Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 541 The ADCH bits form a 5-bit field that selects one of the input channels. 00000-01111 AD0-AD15 10000-10011 10100-10101 Reserved 10110 Temperature Sensor 10111 Bandgap 11000-11100 Reserved 11101 REFH 11110 REFL 11111 Module disabled NOTE: Reset FIFO in FIFO mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 542: Status And Control Register 2 (Adc_Sc2)
Indicates that ADC result FIFO have at least one valid new data. Indicates that ADC result FIFO have no valid new data. Result FIFO full FFULL Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 543: Status And Control Register 3 (Adc_Sc3)
Short sample time. Long sample time. 3–2 Conversion Mode Selection MODE MODE bits are used to select between 12-, 10-, or 8-bit operation. 8-bit conversion (N=8) Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 544: Status And Control Register 4 (Adc_Sc4)
OR all of compare trigger. AND all of compare trigger. 4–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 545: Conversion Result High Register (Adc_Rh)
ADCH. If the MODE bits are changed, any data in ADC_RH becomes invalid. Address: 10h base + 4h offset = 14h Read Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 546: Conversion Result Low Register (Adc_Rl)
AFDEP. The AD result FIFO can be read via ADC_RH:ADC_RL continuously by the order set in analog input channel FIFO. Address: 10h base + 5h offset = 15h Read Write Reset ADC_RL field descriptions Field Description Conversion Result[7:0] MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 547: Compare Value High Register (Adc_Cvh)
8 bits of the result following a conversion in 12-bit mode. Address: 10h base + 7h offset = 17h Read Write Reset ADC_CVL field descriptions Field Description Conversion Result[7:0] MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 548: Pin Control 1 Register (Adc_Apctl1)
AD3 pin I/O control disabled. ADC Pin Control 2 ADPC2 ADPC2 controls the pin associated with channel AD2. AD2 pin I/O control enabled. AD2 pin I/O control disabled. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 549: Pin Control 2 Register (Adc_Apctl2)
ADPC13 controls the pin associated with channel AD13. AD13 pin I/O control enabled. AD13 pin I/O control disabled. ADC Pin Control 12 ADPC12 ADPC12 controls the pin associated with channel AD12. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 550: Functional Description
ADC_RL). In 10-bit mode, the result is rounded to 10 bits and placed in the data registers (ADC_RH and ADC_RL). In 8-bit mode, the result is rounded to 8 bits and MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 551: Clock Select And Divide Control
When a pin control register bit is set, the following conditions are forced for the associated MCU pin: • The output buffer is forced to its high impedance state. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 552: Hardware Trigger
1s) if software triggered operation is selected. • A hardware trigger (ADHWT) event if hardware triggered operation is selected. • The transfer of the result to the data registers when continuous conversion is enabled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 553: Completing Conversions
• The current conversion and the rest of conversions will be aborted and no new conversion will be initialed, if ADC_SC4[AFDEP] are not all 0s. • A new conversion will be initiated when the FIFO is re-fulfilled upon the levels indicated by the ADC_SC4[AFDEP] bits). MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 554: Power Control
ADCK for continuous conversions cannot be guaranteed when long sample is enabled (ADC_SC3[ADLSMP] = 1). The maximum total conversion time for different conditions is summarized in the table below. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 555 8 MHz, then the conversion time for a single conversion as given below: The number of bus cycles at 8 MHz is: Note The ADCK frequency must be between f minimum and ADCK maximum to meet ADC specifications. ADCK MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 556: Automatic Compare Function
The analog channel must be written to this FIFO in order. The ADC will not start the conversion if the channel FIFO is fulfilled below the level indicated by MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 557 FIFO Read/Write Logic Channel FIFO write pointer Channel FIFO Fulfilled COMPARE Result FIFO write pointer LOGIC FIFO Work Logic Channel FIFO read pointer FIFO conversion start BUS CLK Figure 19-12. FADC FIFO structure MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 558 In continuous conversion in which the ADC_SC1[ADCO] bit is set, the ADC starts next conversion immediately when all conversions are completed. ADC module will fetch the analog input channel from the beginning of analog input channel FIFO. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 559 Start FIFOed Conversion when hardware trigger occurs Hardware Triggered Continuous Conversion (Only need one hardware trigger) COCO = 1 The n AD result store Conversions Completed Figure 19-13. ADC FIFO conversion sequence MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 560: Mcu Wait Mode Operation
If a conversion is in progress when the MCU enters Stop3 mode, it continues until completion. Conversions can be initiated while the MCU is in Stop3 mode by means of the hardware trigger or if continuous conversions are enabled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 561: Initialization Information
ADCK. This register is also used for selecting sample time and low-power configuration. 2. Update status and control register 2 (ADC_SC2) to select the hardware or software conversion trigger and compare function options, if enabled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 562: Pseudo-Code Example
4. Update status and control register 1 (ADC_SC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 563: Pseudo-Code Example
= ADC_R; // read conversion result of channel 3 buffer[1] = ADC_R; // read conversion result of channel 5 buffer[2] = ADC_R; // read conversion result of channel 7 buffer[3] = ADC_R; MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 564: Application Information
V pin. This should be the only ground connection between these supplies if possible. The V pin makes a good single point ground location. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 565: Analog Reference Pins
REFL is equal to or exceeds V , the converter circuit converts the signal to 0xFFF (full scale REFH 12-bit representation), 0x3FF (full scale 10-bit representation) or 0xFF (full scale 8-bit MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 566: Sources Of Error
System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 567 Four samples are required to eliminate the effect of a 1LSB, one-time error. • Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 568: Code Width And Quantization Error
0x3FE code width and its ideal (1 lsb) is used. • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 569: Code Jitter, Non-Monotonicity, And Missing Codes
Missing codes are those values that are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 570 Application information MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 571: Introduction
• Selectable interrupt on rising edge, falling edge, or both rising or falling edges of comparator output • Selectable inversion on comparator output • Up to four selectable comparator inputs • Operational in Stop3 mode MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 572: Modes Of Operation
20.1.2.3 Operation in Debug mode When the MCU is in Debug mode, the ACMP continues operating normally. 20.1.3 Block diagram The block diagram of the ACMP module is shown in the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 573: External Signal Description
Reset value (in bits) page (hex) ACMP Control and Status Register (ACMP_CS) 20.3.1/574 ACMP Control Register 0 (ACMP_C0) 20.3.2/575 ACMP Control Register 1 (ACMP_C1) 20.3.3/575 ACMP Control Register 2 (ACMP_C2) 20.3.4/576 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 574: Acmp Control And Status Register (Acmp_Cs)
ACMP output can be placed onto external pin. ACMOD ACMP MOD Determines the sensitivity modes of the interrupt trigger. ACMP interrupt on output falling edge. ACMP interrupt on output rising edge. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 575: Acmp Control Register 0 (Acmp_C0)
ACMP Negative Input Select External reference 0 External reference 1 Reserved DAC output 20.3.3 ACMP Control Register 1 (ACMP_C1) Address: 2Ch base + 2h offset = 2Eh Read DACEN DACREF DACVAL Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 576: Acmp Control Register 2 (Acmp_C2)
The DAC includes a 64-level DAC (digital to analog converter) and relevant control logic. DAC can select one of two reference inputs, V or on-chip bandgap, as the DAC input V by setting ACMP_C1[DACREF]. After the DAC is enabled, it converts the data MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 577: Setup And Operation Of Acmp
The two parts of ACMP (DAC and CMP) can be set up and operated independently. But if the DAC works as an input of the CMP, the DAC must be configured before the ACMP is enabled. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 578: Resets
When in stop3 mode, a valid edge on ACMP output generates an asynchronous interrupt that can wake the MCU from stop3. The interrupt can be cleared by writing a 0 to the ACMP_CS[ACF] bit. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 579: Introduction
• High sensitivity change with 16-bit resolution register • Configurable up to 4096 scan times. • The auxiliary noise detection mode supplies improved EMC immunity. For electrode design recommendations, refer to AN3863: Designing Touch Sensing Electrodes MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 580: Modes Of Operation
– Electrode Oscillator Reference Clock TSI14 Reference TSI15 Oscillator Interrupt TSI_PENx TSICH Control Hardware Trigger SCNIP Logic Write SWTS “1” EXTCHRG REFCHRG CURSW EOSF TSIIEN Figure 21-1. TSI module block diagram MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 581: External Signal Description
TSI Control and Status Register 3 (TSI_CS3) 21.3.4/586 TSI Pin Enable Register 0 (TSI_PEN0) 21.3.5/587 TSI Pin Enable Register 1 (TSI_PEN1) 21.3.6/588 TSI Counter Register: High (TSI_CNTH) 21.3.7/589 TSI Counter Register: Low (TSI_CNTL) 21.3.8/589 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 582: Tsi Control And Status Register 0 (Tsi_Cs0)
This read-only bit indicates if scan is in progress. When this bit reads zero, there is no scan in progress. When this bit reads set, a scan is in progress. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 583: Tsi Control And Status Register 1 (Tsi_Cs1)
Electrode Oscillator Frequency divided by 2 Electrode Oscillator Frequency divided by 4 Electrode Oscillator Frequency divided by 8 Electrode Oscillator Frequency divided by 16 Electrode Oscillator Frequency divided by 32 Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 584 26 times per electrode 11010 27 times per electrode 11011 28 times per electrode 11100 29 times per electrode 11101 30 times per electrode 11110 31 times per electrode 11111 32 times per electrode MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 585: Tsi Control And Status Register 2 (Tsi_Cs2)
These bits indicate the electrode oscillator charge and discharge current value. 500 nA. 1 μ A. 2 μ A. 4 μ A. 8 μ A. 16 μ A. 32 μ A. 64 μ A. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 586: Tsi Control And Status Register 3 (Tsi_Cs3)
Internal low pass filter is bypassed. xx10 Internal low pass filter with 4.3 MHz -3dB bandwidth. xx11 Internal low pass filter with 0.8 MHz -3dB bandwidth. 11xx Noise detection mode with configurable internal filter. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 587: Tsi Pin Enable Register 0 (Tsi_Pen0)
PEN2 This bit enables the touch sensing input pin. PEN2 is disabled. PEN2 is enabled. PEN1 PEN1 This bit enables the touch sensing input pin. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 588: Tsi Pin Enable Register 1 (Tsi_Pen1)
PEN12 This bit enables the touch sensing input pin. PEN12 is disabled. PEN12 is enabled. PEN11 PEN11 This bit enables the touch sensing input pin. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 589: Tsi Counter Register: High (Tsi_Cnth)
These bits record the accumulated scan counter value ticked by the reference clock with CNTL. 21.3.8 TSI Counter Register: Low (TSI_CNTL) Address: 8h base + 7h offset = Fh Read CNTL Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 590: Functional Description
TSI_CS2[EXTCHRG]. The hysteresis delta voltage is defined in the module electrical specifications present in the device Data Sheet. The figure below shows the voltage amplitude waveform of the electrode capacitance charging and discharging with a programmable current. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 591: Electrode Oscillator And Counter Module Control
21.4.1.2 Electrode oscillator and counter module control The TSI oscillator frequency signal goes through a prescaler defined by the TSI_CS1[PS] and then enters in a modulus counter. TSI_CS1[NSCN] defines the maximum count value of the modulus counter. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 592: Tsi Reference Oscillator
The reference oscillator frequency is given by the following equation: NOTE • The internal reference oscillator must be at least 3 times faster than the external oscillator. • The maximum oscillator frequency is limited within 10 MHz. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 593: Tsi Measurement Result
TSI_CS0[STPE] bit is set, it allows the TSI module to work in stop3 mode. NOTE To get better performance, set other channels as GPIO output mode and output 0 when scanning a channel. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 594: Software And Hardware Trigger
MCU regulator is partially powered down, which is ideally for low-power touch detection. The charge and discharge difference voltage is configurable upon the setting of TSI_CS2[DVOLT]. The following table shows the all the delta voltage configurations. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 595: Current Source
TSI_PENx[PENx] bit. Otherwise, the scan does not work or an invalid result will be asserted. Remember to select the channel number by the TSI_CS3[TSICH] before trigger TSI to work. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 596: End Of Scan
Also the external voltage is biased by vmid voltage with a Rs series resistance. The vmid voltage is defined as V(vmid) = (V(vp) + V(vm))/2. The Rs value is defined by TSI_CS2[EXTCHRG] register bits. See Figure 21-14 more information on noise mode TSI circuit. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 597 STAT<1:0> EXTCHRG NSCN REFCHRG (Count_noise) Cref 16-bit clk_ext TSI_CNTH counter1 TSI_CNTL Noise Mode DVOLT Filter prescaler counter2 clk_ref STAT<1:0> EXTCHRG NSCN Figure 21-13. TSI noise detection mode block diagram MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 598 To determine the noise level, the TSI noise detection algorithm shall be performed by scanning this table following the arrow direction starting at maximum Rs and minimum DVOLT. Rs (Bits) (kΩ) DVOLT (Bits) 0.29 0.43 0.73 1.03 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 599 11. Increase DVOLT to the next level by decrementing TSI_CS2[DVOLT] by 1 and set Rs to the max value, then go to step 4; (It means noise level is higher, so need find high DVOLT) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 600 21-15. Capacitive Noise Noise sense sense sense Figure 21-15. Noise detection/sense algorithm of typical application The following flow chart shows how to detect touch with noise sense and normal capacitive sense. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 601 • The V(vp) and V(vm) thresholds are changed in 34.4 µs (T2). • The Rs series resistance value is changed between 184 kΩ (TSI_CS2[EXTCHRG]=011b) and 32 kΩ (TSI_CS2[EXTCHRG]=101). Because of this Rs change the amplitude of noise waveform change also. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 602 Functional description EXTCHRG[2] EXTCHRG[1] EXTCHRG[3] Figure 21-17. TSI noise detection mode waveform MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 603: Introduction
• Optional feature to reverse input and output data by bit • Optional final complement output of result • High-speed CRC calculation 22.3 Block diagram The following figure is the CRC block diagram. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 604: Modes Of Operation
CRC Polynomial 0 Register (CRC_P0) 22.5.5/607 3065 CRC Polynomial 1 Register (CRC_P1) 22.5.6/608 3066 CRC Polynomial 2 Register (CRC_P2) 22.5.7/608 3067 CRC Polynomial 3 Register (CRC_P3) 22.5.8/609 3068 CRC Control Register (CRC_CTRL) 22.5.9/609 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 605: Crc Data 0 Register (Crc_D0)
CRC 32-bit mode. Only D3 is used to dummy data to CRC. Writing D2 will be ignored when WAS = 0. Address: 3060h base + 1h offset = 3061h Read Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 606: Crc Data 2 Register (Crc_D2)
CRC 32-bit mode. Only D3 is used to dummy data to CRC. Writing D2 will be ignored when WAS = 0. Address: 3060h base + 2h offset = 3062h Read Write Reset CRC_D2 field descriptions Field Description CRC Data Bit 15:8 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 607: Crc Data 3 Register (Crc_D3)
LSB 16-bit of CRC polynomial, which is used in both CRC 16- and 32-bit modes. Address: 3060h base + 4h offset = 3064h Read Write Reset CRC_P0 field descriptions Field Description CRC Polynominal Bit 31:24 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 608: Crc Polynomial 1 Register (Crc_P1)
LSB 16-bit of CRC polynomial, which is used in both CRC 16- and 32-bit modes. Address: 3060h base + 6h offset = 3066h Read Write Reset CRC_P2 field descriptions Field Description CRC Polynominal Bit 15:8 MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 609: Crc Polynomial 3 Register (Crc_P3)
Reverse of Read TOTR These bits identify the reverse of the output data. No reverse. Bit is reversed in byte; No byte is reversed. Reserved. Reserved. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 610: Functional Description
8. Get the checksum from CRC_D2:CRC_D3 when all CRC raw data dummied. 22.6.2 32-bit CRC calculation The following steps show how to start a general 32-bit CRC calculation: 1. Set CRC_CTRL[TCRC] bit to enable 32-bit CRC mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 611: Bit Reverse
CRC data registers. When CRC_CTRL[FXOR] bit is set, the checksum is read by its complement. Otherwise, the raw checksum is accessed. 22.6.5 CCITT compliant CRC example The following code segment shows CCITT CRC-16 compliant example. Example: 22.6.5.1 CCITT CRC-16 compliant example MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 612 CRC_CTRL = 0x00; for ( i = 0 ; i < 128 ; i++ ) CRC_D3 = 'A'; // Dummy 256 `A' CRC_D3 = 'A'; // Get 0xea0b in CRC_D2:CRC_D3 here MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 613: Introduction
• Robust write sequence for counter refresh • Refresh sequence of writing 0xA602 and then 0xB480 within 16 bus clocks • Window mode option for the refresh mechanism • Programmable 16-bit window value MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 614: Block Diagram
Clock Delay Window Compare Logic Protect IRQ Interrupt 128 Bus Cycle 0xC520 Control Status 16-bit Window Register Disable Protect Bit Write Control 0xD928 UPDATE PRES WIN Figure 23-1. WDOG block diagram MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 615: Memory Map And Register Definition
(timeout or illegal write to the watchdog), prior to forcing a reset. After the interrupt vector fetch, the reset occurs after a delay of 128 bus clocks. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 616 Watchdog enabled in chip wait mode. Stop Enable STOP This write-once bit enables the watchdog to operate when the chip is in stop mode. Watchdog disabled in chip stop mode. Watchdog enabled in chip stop mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 617: Watchdog Control And Status Register 2 (Wdog_Cs2)
This write-once field indicates the clock source that feeds the watchdog counter. See the Clock source section. Bus clock. 1 kHz internal low-power oscillator (LPOCLK). 32 kHz internal oscillator (ICSIRCLK). External clock source. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 618: Watchdog Counter Register: High (Wdog_Cnth)
High byte of the Watchdog Counter 23.2.4 Watchdog Counter Register: Low (WDOG_CNTL) See the description of the WDOG_CNTH register. Address: 3030h base + 3h offset = 3033h Read CNTLOW Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 619: Watchdog Timeout Value Register: High (Wdog_Tovalh)
23.2.6 Watchdog Timeout Value Register: Low (WDOG_TOVALL) See the description of the WDOG_TOVALH register. NOTE All the bits reset to 0 in read. Address: 3030h base + 5h offset = 3035h Read TOVALLOW Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 620: Watchdog Window Register: High (Wdog_Winh)
23.2.8 Watchdog Window Register: Low (WDOG_WINL) See the description of the WDOG_WINH register. Address: 3030h base + 7h offset = 3037h Read WINLOW Write Reset WDOG_WINL field descriptions Field Description WINLOW Low byte of Watchdog Window MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 621: Functional Description
In addition, if window mode is used, software must not start the refresh sequence until after the time value set in the WDOG_WINH and WDOG_WINL registers. See the following figure. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 622: Window Mode
The refresh write sequence is a write of 0xA602 followed by a write of 0xB480 to the WDOG_CNTH and WDOG_CNTL registers. The write of the 0xB480 must occur within 16 bus clocks after the write of 0xA602; otherwise, the watchdog resets the MCU. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 623: Example Code: Refreshing The Watchdog
Otherwise, the WDOG uses the reset values by default. If window mode is not used (CS2[WIN] is 0), writing to WDOG_WINH:L is not required to make the new configuration take effect. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 624: Reconfiguring The Watchdog
WDOG_CNT = 0xD928; // write the 2nd unlock word WDOG_TOVAL = 1000; // setting timeout value WDOG_CS2 = WDOG_CS2_CLK_MASK; // setting 1-kHz clock source WDOG_CS1 = WDOG_CS1_EN_MASK; // enable counter running EnableInterrupts; // enable global interrupt MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 625 2.5 periods of the previous clock source and 2.5 periods of the new clock source after the configuration time period (128 bus clocks) ends. This delay ensures a smooth transition before restarting the counter with the new configuration. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 626: Using Interrupts To Delay Resets
NOTE The watchdog can not generate interrupt in Stop3 mode even if CS1[STOP] is set and will not wake the MCU from Stop3 mode. It can generate reset during Stop3 mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 627: Fast Testing Of The Watchdog
4. The watchdog counter times out and forces a reset. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 628: Entering User Mode
As an ongoing test when using the default 1-kHz clock source, software can periodically read the WDOG_CNTH and WDOG_CNTL registers to ensure the counter is being incremented. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 629: Introduction
• Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 630: Background Debug Controller (Bdc)
• Non-intrusive commands can be executed at any time even while the user's program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 631: Bkgd Pin Description
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 632: Communication Details
Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 633 1 0 C Y C L E S H O S T S A M P L E S B K G D P IN Figure 24-3. BDC target-to-host serial bit timing (logic 1) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 634: Bdc Commands
The following table shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in the following table to describe the coding structure of the BDC commands. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 635 TRACE1 Active BDM 10/d Trace 1 user instruction at the address in the PC, then return to active background mode Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 636 • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 637: Bdc Hardware Breakpoint
Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 638: Comparators A And B
• Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 639: Bus Capture Information And Fifo Operation
DBGFL reads needed to initially fill the FIFO. Additional periodic reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 640: Change-Of-Flow Information
There is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 641: Trigger Modes
A Then B ̶ Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 642: Hardware Breakpoints
CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 643: Memory Map And Register Description
The reset values shown in the register figure are those in the normal reset conditions. If the MCU is reset in BDM, ENBDM, BDMACT, CLKSW will be reset to 1 and others all be to 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 644 BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands. Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 645: Bdc Breakpoint Match Register: High (Bdc_Bkpth)
Breakpoints are normally set while the target MCU is in active background mode before running the user application program. Address: 0h base + 1h offset = 1h Read A[15:8] Write Reset BDC_BKPTH field descriptions Field Description A[15:8] High 8-bit of hardware breakpoint address. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 646: Bdc Breakpoint Register: Low (Bdc_Bkptl)
BDC_SBDFR field descriptions Field Description 7–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Background Debug Force Reset BDFR Table continues on the next page... MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 647 A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 648 Memory map and register description MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 649: Introduction
• Event only B, store data • A then event only B, store data • Inside range, A ≤ address ≤ B • Outside range, address < A or address > B MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 650: Modes Of Operation
MCU is secure. The DBG module comparators are disabled when executing a Background Debug Mode (BDM) command. 25.1.3 Block diagram The following figure shows the structure of the DBG module. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 651: Signal Description
Figure 25-1. DBG block diagram 25.2 Signal description The DBG module contains no external signals. 25.3 Memory map and registers This section provides a detailed description of all DBG registers accessible to the end user. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 652: Debug Comparator A High Register (Dbg_Cah)
DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset. Address: 3010h base + 0h offset = 3010h Read CA[15:8] Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 653: Debug Comparator A Low Register (Dbg_Cal)
The Comparator A Low compare bits control whether Comparator A will compare the address bus bits [7:0] to a logic 1 or logic 0. Compare corresponding address bit to a logic 0. Compare corresponding address bit to a logic 1. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 654: Debug Comparator B High Register (Dbg_Cbh)
DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset. Address: 3010h base + 3h offset = 3013h Read CB[7:0] Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 655: Debug Comparator C High Register (Dbg_Cch)
The Comparator C High compare bits control whether Comparator C will compare the address bus bits [15:8] to a logic 1 or logic 0. Compare corresponding address bit to a logic 0. Compare corresponding address bit to a logic 1. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 656: Debug Comparator C Low Register (Dbg_Ccl)
DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset. Address: 3010h base + 6h offset = 3016h Read F[15:8] Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 657: Debug Fifo Low Register (Dbg_Fl)
DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX and DBGFH so it is not necessary to read them before reading DBGFL. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 658: Debug Comparator A Extension Register (Dbg_Cax)
The RWA bit controls whether read or write is used in compare for Comparator A. The RWA bit is not used if RWAEN = 0. Write cycle will be matched. Read cycle will be matched. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 659: Debug Comparator B Extension Register (Dbg_Cbx)
RWBEN = 0.In full modes, RWAEN and RWA are used to control comparison of R/W and RWB is ignored. Write cycle will be matched. Read cycle will be matched. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 660: Debug Comparator C Extension Register (Dbg_Ccx)
RWCEN = 0. Write cycle will be matched. Read cycle will be matched. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 661: Debug Fifo Extended Information Register (Dbg_Fx)
This bit is the most significant bit of the 17-bit core address. 25.3.13 Debug Control Register (DBG_C) Address: 3010h base + Ch offset = 301Ch Read DBGEN BRKEN LOOP1 Write Reset MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 662: Debug Trigger Register (Dbg_T)
In the case of an end- trace to reset where DBGEN=1 and BEGIN=0, the ARM and BRKEN bits are cleared but the remaining control bits in this register do not change after reset. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 663 Event only B. 0100 A then event only B. 0101 A and B (full mode). 0110 A and not B (full mode). 0111 Inside range. 1000 Outside range. 1001-1111 No trigger. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 664: Debug Status Register (Dbg_S)
The ARMF bit indicates whether the debugger is waiting for trigger or waiting for the FIFO to fill. While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. Debugger not armed. Debugger armed. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 665: Debug Count Status Register (Dbg_Cnt)
1 word valid. 0010 2 words valid. 0011 3 words valid. 0100 4 words valid. 0101 5 words valid. 0110 6 words valid. 0111 7 words valid. 1000 8 words valid. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 666: Functional Description
FIFO buffer. In loop1 capture mode, comparator C is not available for use as a normal hardware breakpoint. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 667: Breakpoints
DBG_C[TAG] affect all three comparators. When DBG_C[BRKEN] = 0, no CPU breakpoints are enabled. When DBG_C[BRKEN] = 1, CPU breakpoints are enabled and the DBG_C[TAG] bit determines whether the breakpoints will be tag-type or force-type MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 668: Trigger Selection
CPU break will be a tag-type or force-type breakpoint. When DBG_T[TRGSEL] is set, the R/W qualified comparator match signal also passes through the opcode tracking logic. If/when it propagates through this logic, it will cause a MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 669: Begin- And End-Trigger
DBG_C[ARM] is written to zero or when the DBG_C[DBGEN] bit is low. The TBC logic determines whether a trigger condition has been met based on the trigger mode and the trigger selection. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 670: Trigger Modes
B is compared. When the match condition for A or B is met, the corresponding flag in the DBG_S register is set. The A then event only B trigger mode is considered a begin-trigger type and the DBG_T[BEGIN] bit is ignored. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 671 25.4.4.3.9 Outside range, address < A or address > B In the outside range trigger mode, if the match condition for A or B is met, the corresponding flag in the DBGS register is set. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 672: Fifo
Start FIFO at trigger address, force CPU breakpoint when FIFO full Start FIFO at trigger opcode (No CPU breakpoint - keep running) Start FIFO at trigger opcode, force CPU breakpoint when FIFO full MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 673: Storing Data In Fifo
DBG_C[ARM] and DBG_S[ARMF] will be cleared and no more data will be stored. In non-event only end-trigger modes, if the trigger is at a change of flow address the trigger event will be stored in the FIFO. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 674: Reading Data From Fifo
In this scenario, the FIFO captures MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 675 16-bit CPU address 0xFFFE appears during the reset vector fetch • DBG_C = 0xC0 to enable and arm the DBG module • DBG_T = 0x40 to select a force-type trigger, a BEGIN trigger, and A-only trigger mode MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 676 Resets MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 677 • Added a note and updated the examples in the Pseudo-code example Analog comparator (ACMP) • Corrected ACMPF to ACF in the description of ACMP_CS[ACF] Touch Sense Input (TSI) • Updated features in the Features MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 678 • Updated the examples in the TSI electrode oscillator, Electrode oscillator and counter module control, TSI reference oscillator TSI measurement result • Updated the table of the Table 21-12 • Updated Noise detection mode. MC9S08PT60 Reference Manual, Rev. 4, 08/2014 Freescale Semiconductor, Inc.
Page 679 Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. © 2011-2014 Freescale Semiconductor, Inc. Document Number MC9S08PT60RM Revision 4, 08/2014...

Freescale Semiconductor MC9S08PT60 Reference Manual

Chapter 1 Device Overview

Chapter 2 Pins and Connections

Chapter 3 Power Management

Chapter 4 Memory Map

Chapter 5 Interrupt

Chapter 6 System Control

Chapter 7 Parallel Input/Output

Chapter 8 Clock Management

Chapter 9 Chip Configurations

Chapter 10 Central Processor Unit

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