Idcode Instruction - Freescale Semiconductor MCF54455 Reference Manual

IEEE 1149.1 Test Access Port (JTAG)
Instruction
EXTEST
ENABLE_TEST_CTRL
HIGHZ
CLAMP
BYPASS
Reserved
1
Freescale reserves the right to change the decoding of the unused opcodes in the future.
35.4.3.1

IDCODE Instruction

The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path between the
TDI and TDO pin. This instruction allows interrogation of the MCU to determine its version number and
other part identification data. The shift register lsb is forced to logic 1 on the rising edge of TCLK
following entry into the capture-DR state. Therefore, the first bit to be shifted out after selecting the
IDCODE register is always a logic 1. The remaining 31 bits are also forced to fixed values on the rising
edge of TCLK following entry into the capture-DR state.
IDCODE is the default instruction placed into the instruction register when the TAP resets. Thus, after a
TAP reset, the IDCODE register is selected automatically.
35.4.3.2 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction has two functions:
• SAMPLE - See Section 35.4.3.3, "SAMPLE Instruction,"
• PRELOAD - initialize the boundary scan register update cells before selecting EXTEST or
CLAMP. This is achieved by ignoring the data shifting out on the TDO pin and shifting in
initialization data. The update-DR state and the falling edge of TCLK can then transfer this data to
the update cells. The data is applied to the external output pins by the EXTEST or CLAMP
instruction.
35.4.3.3 SAMPLE Instruction
The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input
pins and before the boundary scan cell at the output pins. This sampling occurs on the rising edge of TCLK
in the capture-DR state when the IR contains the 0x2 opcode. The sampled data is accessible by shifting
it through the boundary scan register to the TDO output by using the shift-DR state. The data capture and
the shift operation are transparent to system operation.
35-8
Table 35-5. JTAG Instructions (continued)
IR[4:0]
00100 Selects boundary scan register while applying preloaded values to output
pins and asserting functional reset
00110 Selects TEST_CTRL register
01001 Selects bypass register while tri-stating all output pins and asserting
functional reset
01100 Selects bypass while applying fixed values to output pins and asserting
functional reset
11111 Selects bypass register for data operations
1
all others Decoded to select bypass register
Instruction Summary
for description of this function.
Freescale Semiconductor