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26.5.5
User Initialization (After Setting ECRn[ETHER_EN])
After setting ECRn[ETHER_EN], you can set up the buffer/frame descriptors and write to TDARn and
RDARn. Refer to
Section 26.5.1, "Buffer Descriptors,"
26.5.6
Network Interface Options
The FECs support an MII and reduced MII interface for 10/100 Mbps Ethernet, as well as a 7-wire serial
interface for 10 Mbps Ethernet. The RCRn[MII_MODE] and RCR [RMII_MODE] bits selects the
interface mode. In MII mode (RCRn[MII_MODE] set and RCR [RMII_MODE] cleared), there are 18
signals defined by the IEEE 802.3 standard and supported by the EMAC.
In RMII mode (RCR [MII_MODE] set and RCR [RMII_MODE] cleared), the EMAC supports 8
n
external signals. These signals are shown in
Freescale Semiconductor
Table 26-34. Microcontroller Initialization (continued)
Description
Initialize Transmit Ring Pointer
Initialize Receive Ring Pointer
Initialize FIFO Count Registers
Table 26-35. MII Mode
Signal Description
Transmit Clock
Transmit Enable
Transmit Data
Transmit Error
Collision
Carrier Sense
Receive Clock
Receive Data Valid
Receive Data
Receive Error
Management Data Clock
Management Data
Input/Output
n
Table 26-36
Fast Ethernet Controllers (FEC0 and FEC1)
for more details.
n
n
Table 26-35
EMAC pin
FECn_TXCLK
FECn_TXEN
FECn_TXD[3:0]
FECn_TXER
FECn_COL
FECn_CRS
FECn_RXCLK
FECn_RXDV
FECn_RXD[3:0]
FECn_RXER
FECn_MDC
FECn_MDIO
below.
shows these signals.
26-36
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