Freescale Semiconductor MCF54455 Reference Manual page 90

Table 3-9. D0 Hardware Configuration Info Field Description (continued)
Field
12 FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core.
FPU 0 FPU execute engine not present in core. (This is the value used for this device.)
1 FPU execute engine is present in core.
11–8 Reserved.
7–4 ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core.
ISA 0000 ISA_A
0001 ISA_B
0010 ISA_C (This is the value used for this device.)
1000 ISA_A+
Else Reserved
3–0 Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core.
DEBUG 0000 DEBUG_A
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
1001 DEBUG_B+
1011 DEBUG_D+ (This is the value used for this device.)
1111 DEBUG_D+PST Buffer
Else Reserved
Information loaded into D1 defines the local memory hardware configuration as shown in the figure below.
BDM: Load: 0x081 (D1)
Store: 0x181 (D1)
31 30 29
R CLSZ
W
Reset 0 0 0
15 14 13
R MBSZ CPES DCAS
W
Reset 0 0 1
Freescale Semiconductor
28 27 26 25
ICAS ICSZ
0 0 1 1
12 11 10 9
DCSZ
0 0 1 1
Figure 3-13. D1 Hardware Configuration Info
Description
24 23 22 21
0 0 0
0 0 0 0
8 7 6 5
SRAMSZ
0 0 1 1
ColdFire Core
Access: User read-only
BDM read-only
20 19 18 17
0 0 0 0
0 0 0 0
4 3 2 1
0 0
1 0 0 0
3-24
16
0
0
0
0
0