Signal Descriptions - Freescale Semiconductor MCF54455 Reference Manual

Revision D+ adds the ignore pending interrupt bit (CSR[IPI]) for debug revision D. (This bit is included
in revision A, B, and B+). For revision D+, the revision level (CSR[HRL]) is 0xB.
The following table summarizes the various debug revisions.
Revision CSR[HRL]
A 0000
B 0001
B+ 1001
C 0010
D 0011
D+ 1011
34.2

Signal Descriptions

Table 34-2 describes debug module signals. All ColdFire debug signals are unidirectional and related to a
rising edge of the processor core's clock signal. The standard 26-pin debug connector is shown in
Section 34.4.6, "Freescale-Recommended BDM
Signal
Development Serial Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two
Clock (DSCLK) consecutive rising bus clock edges.) Clocks the serial communication port to the debug module
during packet transfers. Maximum frequency is 1/5 the processor status clock (PSTCLK). At the
synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.
Development Serial Internally synchronized input that provides data input for the serial communication port to the debug
Input (DSI) module after the DSCLK has been seen as high (logic 1).
Development Serial Provides serial output communication for debug module responses. DSO is registered internally. The
Output (DSO) output is delayed from the validation of DSCLK high.
Breakpoint (BKPT) Input requests a manual breakpoint. Assertion of BKPT puts the processor into a halted state after
the current instruction completes. Halt status is reflected on processor status/debug data signals
(PSTDDATA[7:0]) as multiple cycles of 0xF. If CSR[BKD] is set (disabling normal BKPT functionality),
asserting BKPT generates a debug interrupt exception in the processor.
Freescale Semiconductor
Table 34-1. Debug Revision Summary
— Initial debug revision
— BDM command execution does not affect hardware breakpoint logic
Added BDM address attribute register (BAAR)
BKPT configurable interrupt (CSR[BKD])
Level 1 and level 2 triggers on OR condition, in addition to AND
_ command to display the processor's current PC
SYNC PC
— 3 additional PC breakpoint registers PBR1–3
— Combined PST and DDATA signals
Adds breakpoint registers
Supports normal interrupt request service during debug
Redefinition of the PST values for the RTS instruction
— MMU enhancements to support ASID
_ command
FORCE TA
— Added CSR[IPI] for revision D
Pinout".
Table 34-2. Debug Module Signals
Enhancements
Description
Debug Module
34-4