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30.2.6
DMA Timer Counters (DTCNn)
The current value of the 32-bit timer counter can be read at anytime without affecting counting. Writes to
DTCNn clear the timer counter. The timer counter increments on the clock source rising edge (internal bus
clock divided by 1, internal bus clock divided by 16, or DTnIN).
Address: 0xFC07_000C (DTCN0)
0xFC07_400C (DTCN1)
0xFC07_800C (DTCN2)
0xFC07_C00C (DTCN3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
Timer counter. Can be read at anytime without affecting counting and any write to this field clears it.
CNT
30.3
Functional Description
30.3.1
Prescaler
The prescaler clock input is selected from the internal bus clock (f
corresponding timer input, DTnIN. DTnIN is synchronized to the internal bus clock, and the
synchronization delay is between two and three internal bus clocks. The corresponding DTMRn[CLK]
selects the clock input source. A programmable prescaler divides the clock input by values from 1 to 256.
The prescaler output is an input to the 32-bit counter, DTCNn.
30.3.2
Capture Mode
Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value when the
corresponding input capture edge detector senses a defined DTnIN transition. The capture edge bits
(DTMRn[CE]) select the type of transition that triggers the capture and sets the timer event register capture
event bit, DTERn[CAP]. If DTERn[CAP] and DTXMRn[DMAEN] are set, a DMA request is asserted. If
DTERn[CAP] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted.
30.3.3
Reference Compare
Each DMA timer can be configured to count up to a reference value. If the reference value is met,
DTERn[REF] is set.
•
If DTMRn[ORRI] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted.
•
If DTMRn[ORRI] and DTXMRn[DMAEN] are set, a DMA request is asserted.
Freescale Semiconductor
CNT (32-bit timer counter value count)
Figure 30-7. DMA Timer Counters (DTCNn)
Table 30-7. DTCNn Field Descriptions
Description
DMA Timers (DTIM0–DTIM3)
Access: User read/write
8
7
6
5
4
3
divided by 1 or 16) or from the
sys/2
2
1
0
30-8
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