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If the external device asserts the external RESET signal for at least four rising FB_CLK edges (3), if the
watchdog timer times out, or if software requests a reset, the reset control logic latches the reset request
internally. At this point the RSTOUT pin is asserted (5). (Even though the external RESET pin needs to
be asserted for only four FB_CLK edges, it may take up to six clocks beyond RESET assertion for
RSTOUT to assert.) The reset control logic waits until the RESET signal is negated (6) and for the PLL to
attain lock (7) before waiting 512 FB_CLK cycles (10) or for the duration of serial boot (9). For non-serial
boot, the reset control logic may latch the chip configuration options from the FB_AD[7:0] pins (11, 11A).
RSTOUT is then negated (12).
If the external RESET signal is asserted by an external device for at least four rising FB_CLK edges during
the 512 count (10) or during the wait for PLL lock (7) or during serial boot (9), the reset flow switches to
(6) and waits for the RESET signal to be negated before continuing.
13.4.2.2
Asynchronous Reset Request
If reset is asserted by an asynchronous internal reset source, such as loss of lock (2) or power-on reset (1),
the reset control logic asserts RSTOUT (4). The reset control logic waits for the PLL to attain lock (7)
before waiting either 512 bus clock cycles (10) or for the duration of serial boot (9). For non-serial boot,
the reset control logic may then latch the chip configuration options from the FB_AD[7:0] pins (11, 11A).
RSTOUT is then negated (12).
If a loss of lock occurs during the 512 bus clock count (10) or during serial boot (9), the reset flow switches
to (7) and waits for the PLL to lock before continuing.
13.4.3
Concurrent Resets
This section describes the concurrent resets. As in the previous discussion references in parentheses refer
to the state numbers in
Figure
13.4.3.1
Reset Flow
If a power-on reset is detected during any reset sequence, the reset sequence starts immediately (1).
If the external RESET pin is asserted for at least four rising FB_CLK edges while waiting for PLL lock or
the 512 cycles or serial boot, the external reset is recognized. Reset processing switches to wait for the
external RESET pin to negate (6).
If a loss-of-lock condition is detected during the 512 cycle wait or during serial boot, the reset sequence
continues after a PLL lock (7).
13.4.3.2
Reset Status Flags
For a POR reset, the RSR[POR] bit is set, and all other RSR flags are cleared even if another type of reset
condition is pending or concurrently asserted.
If other reset sources are asserted after the RSR status bits have been latched (4 or 5), the device is held in
reset (9 or 10) until all sources have negated, and the subsequent sources are not reflected in the RSR
contents.
Freescale Semiconductor
13-4.
Reset Controller Module
13-7
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