Freescale Semiconductor MCF54455 Reference Manual page 168

Access
Invalid (V = 0)
Read (C,W)I1 Read line from memory and
miss update cache;
supply data to processor;
go to valid state.
Read hit (C,W)I2 Not possible.
Write CI3 Read line from memory and
miss update cache;
(copy- write data to cache;
back) go to modified state.
Write WI3 Write data to memory;
miss stay in invalid state.
(write-
through)
Write hit CI4 Not possible.
(copy-
back)
Write hit WI4 Not possible.
(write-
through)
Cache (C,W)I5 No action;
invalidate stay in invalid state.
Cache (C,W)I6( No action;
push C,W)I7 stay in invalid state.
Freescale Semiconductor
Table 6-6. Data Cache Line State Transitions
Current State
Valid (V = 1, M = 0)
(C,W)V1 Read new line from memory
and update cache;
supply data to processor;
stay in valid state.
(C,W)V2 Supply data to processor;
stay in valid state.
CV3 Read new line from memory
and update cache;
write data to cache;
go to modified state.
WV3 Write data to memory;
stay in valid state.
CV4 Write data to cache;
go to modified state.
WV4 Write data to memory and to
cache;
stay in valid state.
(C,W)V5 No action;
go to invalid state.
(C,W)V6 No action;
go to invalid state.
(C,W)V7 No action;
stay in valid state.
Modified (V = 1, M = 1)
CD1 Push modified line to buffer;
read new line from memory
and update cache;
supply data to processor;
write push buffer contents to
memory;
go to valid state.
CD2 Supply data to processor;
stay in modified state.
CD3 Push modified line to buffer;
read new line from memory
and update cache;
write push buffer contents to
memory;
stay in modified state.
WD3 Write data to memory;
stay in modified state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[DCINVA,ICINVA]
before switching modes.
CD4 Write data to cache;
stay in modified state.
WD4 Write data to memory and to
cache;
go to valid state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[DCINVA,ICINVA]
before switching modes.
CD5 No action (modified data
lost);
go to invalid state.
CD6 Push modified line to
memory;
go to invalid state.
CD7 Push modified line to
memory;
go to valid state.
Cache
6-23