Freescale Semiconductor MCF54455 Reference Manual page 890

34.4.1.5.15 Read Debug Module Register (
Read the selected debug module register and return the 32-bit result. The only valid register selection for
the RDMREG command is CSR (DRc=0x00).
Command/Result Formats:
15 14
Command
Result
Table 34-27 shows the definition of DRc encoding.
DRc[5:0]
Command Sequence:
Operand Data: None
Result Data: The contents of the selected debug register are returned as a longword value. The
data is returned most-significant word first.
34.4.1.5.16 Write Debug Module Register (
The operand (longword) data is written to the specified debug module register. All 32 bits of the register
are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU
accesses are performed using the WDEBUG instruction.
Freescale Semiconductor
13 12 11 10
0x2 0xD
Figure 34-45.
RDMREG
Table 34-27. Definition of DRc Encoding—Read
Debug Register Definition
0x00 Configuration/Status
RDMREG
??? MS RESULT
Figure 34-46.
RDMREG
)
RDMREG
9 8 7 6 5
1 0
D[31:16]
D[15:0]
Command/Result Formats
Mnemonic
XXX NEXT CMD
LS RESULT
XXX NEXT CMD
'ILLEGAL' 'NOT READY'
Command Sequence
)
WDMREG
Debug Module
4 3 2 1 0
DRc
CSR
34-48