Freescale Semiconductor MCF54455 Reference Manual page 763

DMA Serial Peripheral Interface (DSPI)
Field
31 Double baud rate. The DBR bit doubles the effective baud rate of the serial communications clock (SCK). This field
DBR is only used in master mode. It effectively halves the baud rate division ratio supporting faster frequencies and odd
division ratios for the serial communications clock (SCK). When the DBR bit is set, the duty cycle of the serial
communications clock (SCK) depends on the value in the baud rate prescaler and the clock phase bit as listed below.
See the BR field below and
the overall baud rate is divided by two or three of the system clock, the continuous SCK enable or the modified timing
format enable bits must not be set.
0 The baud rate is computed normally with a 50/50 duty cycle
1 Baud rate is doubled with the duty cycle depending on the baud rate prescaler
30–27 Frame size. Selects the number of bits transferred per frame. The FMSZ field is used in master mode and slave
FMSZ mode. The table below lists the frame sizes.
31-10
Table 31-5. DSPI_CTARn Field Description
Description
Section 31.4.3.1, "Baud Rate
DBR CPHA
0 any
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
FMSZ Framesize
0000 Reserved
0001 Reserved
0010 Reserved
0011 4
0100 5
0101 6
0110 7
0111 8
Generator" for details on how to compute the baud rate. If
PBR SCK Duty Cycle
any 50/50
00 50/50
01 33/66
10 40/60
11 43/57
00 50/50
01 66/33
10 60/40
11 57/43
FMSZ Framesize
1000 9
1001 10
1010 11
1011 12
1100 13
1101 14
1110 15
1111 16
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