Table of Contents
Advertisement
Power Management
Field
7
Reserved, must be cleared.
6
Set all module clock disables.
SAMCD
0 Set only those bits specified in the SMCD field
1 Set all bits in PPMRH and PPMRL, disabling all peripheral clocks
5–0
Set module clock disable. Set the corresponding bit in PPM{H,L}R, disabling the peripheral clock.
SMCD
9.2.3
Peripheral Power Management Clear Register (PPMCR0)
The PPMCR register provides a simple mechanism to clear a given bit in the PPMHR and PPMLR
registers, enabling the clock for a given peripheral module without needing to perform a read-modify write
on the PPMR. The data value on a register write causes the corresponding bit in the PPM{H,L}R to be
clear. A value of 64 to 127 (setting the CAMCD bit) provides a global clear function, forcing the entire
PPMR contents to clear, enabling all peripheral module clocks. Reads of these registers return all zeroes.
Address: 0xFC04_002D (PPMCR0)
7
R
0
W
Reset:
0
Figure 9-3. Peripheral Power Management Clear Register (PPMCR0)
Field
7
Reserved, must be cleared.
6
Clear all module clock disables.
CAMCD
0 Clear only those bits specified in the CMCD field
1 Clear all bits in PPMRH and PPMRL, enabling all peripheral clocks
5–0
Clear module clock disable. Clear the corresponding bit in PPMR{H,L}, enabling the peripheral clock.
CMCD
9.2.4
Peripheral Power Management Registers (PPMHR0 and PPMLR0)
The PPMR registers provide a bit map for controlling the generation of the peripheral clocks for each
decoded address space. Recall each peripheral module is mapped into 16 kByte slots within the memory
map. The PPMR registers provide a unique control bit for each address space that defines whether the
module clock for the given space is enabled or disabled.
Because the operation of the crossbar switch and the system control module (SCM) are fundamental to the
operation of the device, the clocks for these modules cannot be disabled.
9-4
Table 9-3. PPMSR0 Field Descriptions
6
5
0
0
CAMCD
0
0
Table 9-4. PPMCR0 Field Descriptions
Description
4
3
2
0
0
0
CMCD
0
0
0
Description
Access: Supervisor Write-only
1
0
0
0
0
0
Freescale Semiconductor
Advertisement
Table of Contents
