Initialization/Application Information - Freescale Semiconductor MCF54455 Reference Manual

The RCR delay module maintains the 1/4 memory clock period delay of the DQS signals across the full
range of silicon process, voltage, and temperature conditions.
The RD_CLK is an internal reconstructed clock derived from DQS. It is twice the frequency of DQS, with
the rising edge shifted 1/4 memory clock period after the DQS edge to align with the nominal center of the
data valid window.
21.6

Initialization/Application Information

SDRAMs have a prescribed initialization sequence. The following sections detail the memory
initialization steps for DDR SDRAM, mobile DDR, and DDR2 SDRAM. The sequence might change
ghtly from device-to-device. Refer to the SDRAM manufacturer's device datasheet as the most relevant
reference.
21.6.1 DDR SDRAM Initialization Sequence
1. After reset is deactivated, pause for the amount of time indicated in SDRAM specification. Usually
200s.
2. Configure pin multiplex control for shared SD_CS pins in pin multiplexing and control module if
needed.
3. Configure the slew rate for the SDRAM external pins in the pin multiplexing and control module's
MSCR_SDRAM register if needed.
4. Write the SDCSn register values for each chip select that is used.
5. Program SDRAM configuration registers (SDCFG1 and SDCFG2) with correct delay and timing
values.
6. Issue a command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] and
PALL
SDCR[MODE_EN] set. The SDCR[REF and IREF] bits should remain cleared for this step.
7. Initialize the SDRAM's extended mode register to enable the DLL. See
Mode/Extended Mode Register Command (lmr, lemr),"
command.
8. Initialize the SDRAM's mode register and reset the DLL using the
Section 21.5.1.6, "Load Mode/Extended Mode Register Command (lmr, lemr),"
instruction on issuing a
should be set to normal operation/reset DLL.
9. Pause for the DLL lock time specified by the memory.
10. Issue a second
PALL
and SDCR[MODE_EN] set. The SDCR[REF and IREF] bits should remain cleared for this step.
11. Refresh the SDRAM. The SDRAM specification should indicate a number of refresh cycles to be
performed before issuing an
MODE_EN bits set (SDCR[REF and IPALL] must be cleared). This forces a refresh of the
SDRAM each time the IREF bit is set. Repeat this step until the specified number of refresh cycles
have been completed.
Freescale Semiconductor
command. During this step the OP_MODE field of the mode register
LMR
command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL]
command (usually two). Write to the SDCR with the IREF and
LMR
SDRAM Controller (SDRAMC)
Section 21.5.1.6, "Load
for instructions on issuing a
command. See
LMR
LEMR
for more
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