Freescale Semiconductor MCF54455 Reference Manual page 297

Chip Configuration Module (CCM)
Field
10–8 Bus monitor timing field. Selects the timeout period in FlexBus clock cycles for the bus monitor:
BMT Timeout period for external bus cycles equals 2
000 65536
001 32768
010 16384
011 8192
100 4096
101 2048
110 1024
111 512
7 SSI RXD/TXD pull enable. Enables the internal weak pull cells on any external pin where either the SSI receive
SSIPUE data (RXD) function or SSI transmit data (TXD) function is available. The affected pins include SSI_RXD, and
SSI_TXD.
0 SSI data pin weak pull cells disabled.
1 SSI data pin weak pull cells enabled.
Note: The SSIPUE bit enables only the pull cells when the SSI RXD and TXD functions are currently selected
for the affected pins. See the
the SSI functions on those pins.
6 SSI RXD/TXD pull select. Selects whether the internal weak pull cells enabled by the SSIPUE bit are pull up or
SSIPUS pull down.
0 SSI data pins are pulled down.
1 SSI data pins are pulled up.
Note: The SSIPUS bit has no effect when the SSIPUE bit is cleared.
5 Timer DMA mux selection. Selects between the timer DMA signals and SSI DMA signals as those signals are
TIMDMA mapped to DMA channels 9-12. Refer to the
details on the DMA controller.
0 SSI RX0, SSI RX1, SSI TX0, and SSI TX1 DMA signals mapped to DMA channels 9 – 12, respectively.
1 Timer 0 – 3 DMA signals mapped to DMA channels 9 – 12, respectively.
4 SSI clock source. Selects between the PLL and the external SSI_CLKIN pin as the source of the SSI baud clock.
SSISRC 0 SSI_CLKIN pin directly drives SSI baud clock.
1 PLL drives SSI baud clock with fractionally divided CPU clock.
3 Reserved, must be cleared.
2 USB transceiver pull-up disable. Disables the USB OTG controller from driving the internal transceiver pull-up.
USBPUD 0 USB OTG drives the internal transceiver pull-up.
1 Internal transceiver pull-up is disabled. The USB_PULLUP signal is used to trigger the external pull-up.
1 USB VBUS over-current sense polarity. Selects the polarity of the USB VBUS over-current sense signal driven
USBOC off-chip.
0 USB_VBUS_OC is active high.
1 USB_VBUS_OC is active low.
0 USB clock source. Selects between the PLL and the external USB_CLKIN external pin as the clock source for
USBSRC the serial and ULPI interfaces of the USB module.
0 USB_CLKIN pin drives USB serial interface clocks.
1 PLL drives USB serial interface clocks.
11-10
Table 11-8. MISCCR Field Descriptions (continued)
Chapter 16, "Pin Multiplexing and Control,"
Chapter 19, "Enhanced Direct Memory Access (eDMA),"
Description
(16-BMT)
FB_CLK cycles
for information on how to enable
for more
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