Mmu Status Register (Mmusr) - Freescale Semiconductor MCF54455 Reference Manual

Field
3 TLB address select. Indicates which address to use when accessing the TLB.
ADR 0 Use the TLB allocation address for the TLB address
1 Use MMUAR for the TLB address
2 TLB access read/write select. Indicates whether to perform a read or a write when accessing the TLB.
R/W 0 Write
1 Read
1 MMU TLB access. This bit always reads as a zero. STLB is used for search operations.
ACC 0 No operation. ACC must be a zero to search the TLB.
1 The MMU reads or writes the TLB depending on R/W. For TLB reads, TLB tag and data results are loaded into
MMUTR and MMUDR. For TLB writes, the contents of these registers are written to the TLB. The TLB is
accessed using the TLB allocation address if ADR is zero or using MMUAR if ADR is set.
0 Update allocation address. UAA always reads as a zero.
UAA 0 No operation
1 MMU updates the allocation address field with the MMU's choice for the allocation address in the ITLB or DTLB
depending on the ITLB instruction operation bit.
4.2.5

MMU Status Register (MMUSR)

MMUSR is updated on all data access faults and search TLB operations.
MMUBAR 0x008 (MMUSR)
Offset:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–6 Reserved, must be cleared.
5 Supervisor-protect fault. Indicates if last data fault was a user-mode access that hit in a TLB entry with its
SPF supervisor protect bit set.
0 Last data access fault did not have a supervisor protect fault
1 Last data access fault had a supervisor protect fault
4 Read-access fault. Indicates if last data fault was a data-read access that hit in a TLB entry without its read bit set.
RF 0 Last data access fault did not have a read protect fault
1 Last data access fault had a read protect fault
3 Write-access fault. Indicates if the last data fault was a data-write access that hit in a TLB entry without its write
WF bit set.
0 Last data access fault did not have a write protect fault
1 Last data access fault had a write protect fault
2 Reserved, must be cleared.
Freescale Semiconductor
Table 4-5. MMUOR Field Descriptions (continued)
Figure 4-6. MMU Status Register (MMUSR)
Table 4-6. MMUSR Field Descriptions
Description
9 8
Description
Memory Management Unit (MMU)
Access: User read/write
7 6 5 4 3 2 1
0
SPF RF WF HIT
0 0 0 0 0
4-7
0
0
0