Freescale Semiconductor MCF54455 Reference Manual page 892

Table 34-28. PSTDDATA Nibble/CSR[BSTAT] Breakpoint Response
PSTDDATA
Nibble
0000
0010
0100
1010
1100
1
Encodings not shown are reserved for future use.
The breakpoint status is also posted in the CSR. CSR[BSTAT] is cleared by a CSR read when a level-2
breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. Status
is also cleared by writing to either TDR or XTDR to disable trigger options.
BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates,
a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner—exception recognition and processing are initiated before
the excepting instruction executes. All other breakpoint events are recognized on the processor's local bus,
but are made pending to the processor and sampled like other interrupt conditions. As a result, these
interrupts are imprecise.
In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] equals 01,
a breakpoint trigger causes the core to halt (PST = 0xF).
If the processor core cannot be halted, the debug interrupt can be used. With this configuration,
TDR[TRC] equals 10, breakpoint trigger becomes a debug interrupt to the processor, which is treated
higher than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the
processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC
breakpoint to occur before the targeted instruction executes and is precise. This is possible because the PC
breakpoint is enabled when interrupt sampling occurs. For address and data breakpoints, reporting is
considered imprecise, because several instructions may execute after the triggering address or data is
detected.
As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception
processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for
multiple cycles. The core enters emulator mode when exception processing begins. After the standard
8-byte exception stack is created, the processor fetches a unique exception vector from the vector table.
Table 34-29 describes the two unique entries that distinguish PC breakpoints from other trigger events.
Vector Number Vector Offset (Hex)
12
13
Freescale Semiconductor
1
CSR[BSTAT]
1
0000
0001
0010
0101
0110
Table 34-29. Exception Vector Assignments
Stacked Program Counter
0x030 Next
0x034 Next
Breakpoint Status
No breakpoints enabled
Waiting for level-1 breakpoint
Level-1 breakpoint triggered
Waiting for level-2 breakpoint
Level-2 breakpoint triggered
Non-PC-breakpoint debug interrupt
PC-breakpoint debug interrupt
Debug Module
Assignment
34-50