Freescale Semiconductor MCF54455 Reference Manual page 197

Power Management
Address: 0xFC04_0034 (PPMLR0)
31 30 29
R
CD31 CD30 CD29 CD28
W
Reset 0 0 0
15 14 13
R 0
CD15 CD13 CD12
W
Reset 0 0 0
Figure 9-5. Peripheral Power Management Low Registers (PPMLR0)
Slot Number
Field
CDn Module slot n clock disable.
0 The clock for this module is enabled.
1 The clock for this module is disabled.
9-6
28 27 26 25
0
CD26 CD25 CD24 CD23 CD22 CD21
0 0 0 0
12 11 10 9
0 0 0
0 0 0 0
Table 9-6. PPMLR0[CDn] Assignments
CDn
2 CD2
12 CD12
13 CD13
15 CD15
17 CD17
18 CD18
19 CD19
21 CD21
22 CD22
23 CD23
24 CD24
25 CD25
26 CD26
28 CD28
29 CD29
30 CD30
31 CD31
Table 9-7. PPMHR and PPMLR Field Descriptions
24 23 22 21
0 0 0 0
8 7 6 5
0 0 0 0
0 0 0 0
Peripheral
FlexBus
FEC0
FEC1
Real-Time Clock
eDMA Controller
Interrupt Controller 0
Interrupt Controller 1
IACK
2
I C
DSPI
UART0
UART1
UART2
DMA Timer 0
DMA Timer 1
DMA Timer 2
DMA Timer 3
Description
Access: Supervisor read/write
20 19 18 17
0
CD19 CD18 CD17
0 0 0 0
4 3 2 1
0 0 0
CD2
0 0 0 0
Freescale Semiconductor
16
0
0
0
0
0