Freescale Semiconductor MCF54455 Reference Manual page 543

PCI Bus Controller
22.3.3.1 PCI Arbiter Control Register (PACR)
Address: 0xFC0A_C000 (PACR)
31 30 29
R 0
DS PKMD
W
Reset 1 0 0
15 14 13
R 0 0
RA
W
Reset 0 0 0
Field
31 Disable. Disables the internal PCI arbiter.
DS 0 Enable the PCI arbiter.
1 Disable the on-chip arbiter and use PCI_GNT[0] for the PCI controller request output and PCI_REQ[0] for its
grant input.
30 Parking mode. Controls which master takes bus ownership when no device uses or requests the bus.
PKMD 0 Park with last master to use the bus.
1 Park with PCI controller.
29–21 Reserved, must be cleared.
20–17 External master broken interrupt enables. If an external master time-out occurs and the corresponding interrupt
EXTMINTEN enable bit is set, a CPU interrupt generates. Bit 20 is the enable for PASR bit 20, bit 19 for PASR bit 19, and so on.
0 Disable interrupt
1 Enable interrupt
Software must write 1 to the corresponding PASR[EXTMBK] bit to clear the interrupt condition.
16 Internal master broken interrupt enable. If a PCI Controller master time-out occurs (PASR[ITLMBK]) and this bit
INTMINTEN is set, a CPU interrupt generates.
0 Disable interrupt
1 Enable interrupt
Software must write 1 to the PASR[ITLMBK] bit to clear the interrupt condition.
15 Reset arbiter. Puts the PCI arbiter in a reset state. Other PACR register bits are not affected, but all bits PASR
RA register are cleared. If the PCI arbiter detects any broken masters when this bit is set, ignore condition clears.
When this bit subsequently clears, requests from broken masters are once again recognized and arbitration
resumes.
This reset bit does not prohibit register access, but it must be cleared for arbitration to occur. When set, the arbiter
parks with the internal master.
14–5 Reserved, must be cleared.
22-26
28 27 26 25
0 0 0 0
0 0 0 0
12 11 10 9
0 0 0 0
0 0 0 0
Figure 22-33. PACR Register
Table 22-23. PACR Field Descriptions
24 23 22 21
0 0 0 0
0 0 0 0
8 7 6 5
0 0 0 0
0 0 0 0
Description
Access: User read/write
20 19 18 17
EXTMINTEN
MINTEN
0 0 0 0
4 3 2 1
EXT_MPRI
MPRI
0 0 0 0
Freescale Semiconductor
16
INT
0
0
INT
0