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Programming Sheets
Application:
Central Processor
Unnormalized ( U = Acc(47) xnor Acc(46) )
Extension
Limit
FFT Scaling ( S = Acc(46) xor Acc(45) )
Scaling Mode
S(1:0)
Scaling Mode
00
No scaling
01
Scale down
10
Scale up
11
Reserved
Reserved
Sixteen-Bit Compatibilitity
Double Precision Multiply Mode
Loop Flag
DO-Forever Flag
Sixteenth-Bit Arithmetic
Reserved
Instruction Cache Enable
Arithmetic Saturation
Rounding Mode
Core Priority
CP(1:0)
Core Priority
00
0 (lowest)
01
1
10
2
11
3 (highest)
23 22
21 20
CP1 CP0 RM
SM
Extended Mode Register (MR)
Status Register (SR)
D-16
Interrupt Mask
I(1:0)
Exceptions Masked
00
None
01
IPL 0
10
IPL 0, 1
11
IPL 0, 1, 2
19 18 17 16
15 14 13 12 11 10
CE
SA
FV
LF
DM
*
0
Mode Register (MR)
Read/Write
Reset = $C00300
Figure D-1. Status Register (SR)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Carry
Overfow
Zero
Negative
9
8
SC
S1
S0
I1
I0
*
0
Date:
:
Programmer
Sheet 1 of 5
7
6
5
4
3
2
S
L
E
U
N
Z
Condition Code Register (CCR)
= Reserved, Program as 0
*
Freescale Semiconductor
1
0
V
C
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