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Freescale Semiconductor MPC8349EA PowerQUICC II Pro Hardware Specifications

Integrated host processor
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Technical Data
MPC8349EA PowerQUICC™ II Pro
Integrated Host Processor Hardware

Specifications

The MPC8349EA contains a PowerPC™ processor core
(built on Power Architecture™ technology) with system
logic for networking, storage, and general-purpose
embedded applications. For functional characteristics of the
processor, refer to the MPC8349EA PowerQUICC™ II Pro
Integrated Host Processor Reference Manual.
To locate published errata or updates for this document,
contact your Freescale sales office.
The information in this document is accurate
for revision 3.0 silicon and later. For
information on revision 1.1 silicon and earlier
versions, see the MPC8349E
PowerQUICC™ II Pro Integrated Host
Processor Hardware Specifications. See
Section 23.1, "Part Numbers Fully
Addressed by this
revision level determination.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
NOTE
Document," for silicon
MPC8349EAEC
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 21
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 24
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 75
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
21. System Design Information . . . . . . . . . . . . . . . . . . 103
22. Document Revision History . . . . . . . . . . . . . . . . . . 109
23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 109
Rev. 2, 8/2006

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Summary of Contents for Freescale Semiconductor MPC8349EA PowerQUICC II Pro

  • Page 1: Table Of Contents

    Document,” for silicon 23. Ordering Information ..... . . 109 revision level determination. © Freescale Semiconductor, Inc., 2006. All rights reserved.

  • Page 2: Overview

    — Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable — DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports — Full error checking and correction (ECC) support MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 3 — Accesses to all PCI address spaces — Parity supported — Selectable hardware-enforced coherency — Address translation units for address mapping between host and peripheral — Dual address cycle for target MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 4 – One upstream facing port – Six programmable USB endpoints — Can operate as a stand-alone USB host controller – USB root hub with one downstream-facing port MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 5 Dual industry-standard I C interfaces — Two-wire interface — Multiple master support — Master or slave I C mode support — On-chip digital filtering rejects spikes on the bus MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 6 — Software watchdog timer — Eight general-purpose timers • Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan • Integrated PCI bus and SDRAM clock generation MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 7: Electrical Characteristics

    Figure 6. OV on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 8 Not to Exceed 10% of t interface Note: 1. t refers to the clock period associated with the bus clock interface. interface Figure 2. Overshoot/Undershoot Voltage for GV MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 9: Rev.

    = 1.8 V 32 (half strength mode) TSEC/10/100 signals = 2.5/3.3 V DUART, system control, I2C, JTAG = 3.3 V GPIO signals = 3.3 V, = 2.5/3.3 V MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 10: Power Sequencing

    I/O pins are tri-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 11 Electrical Characteristics MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 12: Power Characteristics

    Maximum Power is based on a voltage of Vdd = 1.2 V, worst case process, a junction temperature of T = 105°C, and an artificial smoke test. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 13 GMII or TBI 0.06 Load = 25 pf RGMII or RTBI 0.04 12 MHz 0.01 Multiply by 2 if using 2 ports. 480 MHz Other I/O 0.01 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 14 Power Characteristics MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 15 Power Characteristics MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 16 Power Characteristics MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 17 Power Characteristics MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 18 Power Characteristics MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 19: Clock Input Timing

    5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 20 Clock Input Timing MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 21: Reset Initialization

    PCI host mode Input setup time for POR configuration signals — PCI_SYNC_IN (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is in PCI agent mode MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 22 8:1 ratio results in the maximum. 2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.” MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 23 RESET Initialization MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 24: Ddr And Ddr2 Sdram

    It is the supply to which far end signal termination is made and is expected to equal . This rail should track variations in the DC level of MV ≤ ≤ 4. Output leakage is measured with all outputs disabled, 0 V MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 25 1. This parameter is sampled. GV = 2.5 V ± 0.125 V, f = 1 MHz, T = 25°C, V = GVDD/2, V (peak-to-peak) = 0.2 V. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 26 At recommended operating conditions with GV of 2.5 ± 5%. Parameter Symbol Unit Notes AC input low voltage — – 0.31 AC input high voltage + 0.31 — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 27 200 MHz 4.20 — MCS(n) output setup with respect to MCK DDKHCS 400 MHz 1.95 — 333 MHz 2.40 — 266 MHz 3.15 — 200 MHz 4.20 — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 28 400 MHz — 333 MHz — 266 MHz 1100 — 200 MHz 1200 — –0.5 × t –0.5 × t MDQS preamble start – 0.6 DDKHMP +0.6 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 29 The timing parameters listed in the table assume that these two parameters are set to the same adjustment value. See the MPC8349EA PowerQUICC II Pro Integrated Processor Reference Manual for the timing modifications enabled by use of these bits.
  • Page 30 Figure 5. DDR SDRAM Output Timing Diagram Figure 6 provides the AC test load for the DDR bus. = 50 Ω Output = 50 Ω Figure 6. DDR AC Test Load MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 31 DDR and DDR2 SDRAM MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 32: Duart

    2. The middle of a start bit is detected as the 8 sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16 sample. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 33 DUART MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 34: Ethernet: Three-Speed Ethernet, Mii Management

    , in this case, represents the LV symbol referenced in Table 1 Table 2. GMII/MII pins not needed for RGMII or RTBI operation are powered by the OVDD supply. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 35 — μA Input low current = GND –15 — Note: 1. The symbol V , in this case, represents the LV symbol referenced in Table 1 Table MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 36 2. This symbol represents the external GTX_CLK125 signal and does not follow the original symbol naming convention. Figure 7 shows the GMII transmit AC timing diagram. GTXR GTX_CLK GTXH GTXF TXD[7:0] TX_EN TX_ER GTKHDX Figure 7. GMII Transmit AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 37 R (rise) or F (fall). Figure 8 shows the GMII receive AC timing diagram. GRXR RX_CLK GRXH GRXF RXD[7:0] RX_DV RX_ER GRDXKH GRDVKH Figure 8. GMII Receive AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 38 (rise) or F (fall). Figure 9 shows the MII transmit AC timing diagram. MTXR TX_CLK MTXH MTXF TXD[3:0] TX_EN TX_ER MTKHDX Figure 9. MII Transmit AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 39 Figure 11 shows the MII receive AC timing diagram. MRXR RX_CLK MRXH MRXF RXD[3:0] RX_DV Valid Data RX_ER MRDVKH MRDXKH Figure 11. MII Receive AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 40 2. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention Figure 12 shows the TBI transmit AC timing diagram. TTXR GTX_CLK TTXH TTXF TXD[7:0] TX_EN TX_ER TTKHDX Figure 12. TBI Transmit AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 41 TBI receive AC timing diagram. TRXR PMA_RX_CLK1 TRXH TRXF RCG[9:0] Even RCG Odd RCG TRDVKH TRDXKH SKTRX PMA_RX_CLK0 TRXH TRDXKH TRDVKH Figure 13. TBI Receive AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 42 5. Duty cycle reference is L 6. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 43 (At PHY) RXD[8:5][3:0] RXD[8:5] RXD[3:0] RXD[7:4] RXD[7:4][3:0] SKRGT RXD[9] RXD[4] RX_CTL RXERR RXDV SKRGT RX_CLK (At PHY) Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 44 Input low current = Max = 0.5 V –600 — Note: 1. The symbol V , in this case, represents the LV symbol referenced in Table 1 Table MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 45 333 MHz, the delay is 58 ns). Figure 15 shows the MII management AC timing diagram. MDCR MDCF MDCH MDIO (Input) MDDVKH MDDXKH MDIO (Output) MDKHDX Figure 15. MII Management Interface Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 46 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 47: Usb

    5. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 48 AC test load and signals for the USB, respectively. = 50 Ω Output = 50 Ω Figure 16. USB AC Test Load USB0_CLK/USB1_CLK/DR_CLK USIXKH USIVKH Input Signals USKHOV USKHOX Output Signals: Figure 17. USB Signals MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 49 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 50: Local Bus

    Local bus clock to address valid for LAD — LBKHOV3 Output hold from local bus clock (except LAD/LDP and LALE) — LBKHOX1 Output hold from local bus clock for LAD/LDP — LBKHOX2 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 51 8. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 52 9. DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 18 provides the AC test load for the local bus. = 50 Ω Output = 50 Ω Figure 18. Local Bus C Test Load MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 53 LA[27:31]/LBCTL/LBCKE/LOE/ LBKHOV LBKHOX Output (Data) Signals: LAD[0:31]/LDP[0:3] LBKHOZ LBKHOV LBKHOX Output (Address) Signal: LAD[0:31] LBOTOT LBKHLR LALE Figure 19. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 54 UPM Mode Input Signal: LUPWAIT LBIXKH1 LBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] LBKHOZ1 LBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 55 Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) LBKHOZ LBKHOV UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 56 Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) LBKHOZ LBKHOV UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 57 UPM Mode Input Signal: LUPWAIT LBIXKH1 LBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] LBKHOZ1 LBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 58: Jtag

    Input setup times: — Boundary-scan data JTDVKH — TMS, TDI JTIVKH Input hold times: — Boundary-scan data JTDXKH — TMS, TDI JTIXKH Valid times: Boundary-scan data JTKLDV JTKLOV MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 59 JTAG clock input timing diagram. JTAG External Clock JTKHKL JTGR JTGF VM = Midpoint Voltage (OV DD /2) Figure 26. JTAG Clock Input Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 60 TDI, TMS Data Valid JTKLOV JTKLOX Output Data Valid JTKLOZ Output Data Valid VM = Midpoint Voltage (OV DD /2) Figure 29. Test Access Port Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 61 JTAG MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 62: I2C

    Hold time (repeated) START condition (after this period, the first clock pulse is — I2SXKL generated) Data setup time — I2DVKH μs Data hold time: I2DXKL — — CBUS compatible masters C bus devices MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 63 AC timing diagram for the I C bus. I2CF I2DVKH I2KHKL I2CF I2CL I2SXKL I2CR I2SXKL I2CH I2SVKH I2PVKH I2DXKL Figure 31. I C Bus AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 64 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 65: Pci

    — PCKHOX Clock to output high impedance — 2, 3 PCKHOZ Input setup to Clock — 2, 4 PCIVKH Input hold from Clock — 2, 4 PCIXKH MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 66 4. Input timings are measured at the pin. 5. The setup and hold time is with respect to the rising edge of PORESET. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 67 Figure 33. PCI Input AC Timing Diagram Figure 34 shows the PCI output AC timing diagram. PCKHOV PCKHOX Output Delay PCKHOZ High-Impedance Output Figure 34. PCI Output AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 68 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 69: Timers

    2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external synchronous logic. Timer inputs are required to be valid for at least t ns to ensure proper operation. TIWID MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 70: Gpio

    2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external synchronous logic. GPIO inputs must be valid for at least t ns to ensure proper operation. PIWID MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 71 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least t ns to ensure proper operation in edge PICWID triggered mode. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 72: Spi

    (first two letters of functional block)(reference)(state)(signal)(state) NIKHOX internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 73 (See Note) NIKHOX Output Signals: SPIMOSI (See Note) Note: The clock edge is selectable on SPI. Figure 37. SPI AC Timing in Master Mode (Internal Clock) Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 74 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 75: Package And Pin Listings

    Interconnects Pitch 1.00 mm Module height (typical) 1.46 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZU package) 95.5 Sn/0.5 Cu/4Ag (VV package) Ball diameter (typical) 0.64 mm MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 76 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement must exclude any effect of mark on top surface of package. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 77 Package and Pin Listings MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 78 AC31, AC33, AC34, AD30, AD32, AD33, AD34, AE29, AE30, AH32, AH33, AH34, AM33, AJ31, AJ32, AJ33, AJ34, AK32, AK33, AK34, AM34, AL33, AL34, AK31, AH30 PCI2_C/BE[3:0]/ AC32, AE32, AH31, AL32 PCI1_C/BE[7:4] PCI2_PAR/PCI1_PAR64 AG34 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 79 AG2, AG1, AK1, AL4 MCKE[0:1] H3, G1 MCK[0:5] U2, F4, AM3, V3, F2, AN3 MCK[0:5] U3, E3, AN2, V4, E1, AM4 MODT[0:3] AH3, AJ5, AH1, AJ4 MBA[2] MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 80 LGPL2/ AJ24 LSDRAS/LOE LGPL3/LSDCAS/ AN27 cfg_reset_source2 LGPL4/LGTA/LUPWAIT/LPBSE AP28 LGPL5/cfg_clkin_div AL26 LCKE AM27 LCLK[0:2] AN28, AK26, AP29 LSYNC_OUT AM12 LSYNC_IN AJ10 General Purpose I/O Timers GPIO1[0]/DMA_DREQ0/ GTM1_TIN1/ GTM2_TIN2 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 81 GTM1_TIN3/ GTM2_TIN4 GPIO1[7]/DMA_DACK2/ GTM1_TGATE3/ GTM2_TGATE4 GPIO1[8]/DMA_DDONE2/ GTM1_TOUT3 GPIO1[9]/DMA_DREQ3/ GTM1_TIN4/ GTM2_TIN3 GPIO1[10]/DMA_DACK3/ GTM1_TGATE4/ GTM2_TGATE3 GPIO1[11]/DMA_DDONE3/ GTM1_TOUT4/ GTM2_TOUT3 USB Port 1 MPH1_D0_ENABLEN/DR_D0_ ENABLEN MPH1_D1_SER_TXD/DR_D1_ SER_TXD MPH1_D2_VMO_SE0/DR_D2_ VMO_SE0 MPH1_D3_SPEED/DR_D3_SP MPH1_D4_DP/DR_D4_DP MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 82 PCTL0 MPH1_PCTL1/DR_TX_VALIDH _PCTL1 MPH1_CLK/DR_CLK USB Port 0 MPH0_D0_ENABLEN/ DR_D8_CHGVBUS MPH0_D1_SER_TXD/ DR_D9_DCHGVBUS MPH0_D2_VMO_SE0/ DR_D10_DPPD MPH0_D3_SPEED/ DR_D11_DMMD MPH0_D4_DP/ DR_D12_VBUS_VLD MPH0_D5_DM/ DR_D13_SESS_END MPH0_D6_SER_RCV/DR_D14 B31 MPH0_D7_DRVVBUS/DR_D15 _IDPULLUP MPH0_NXT/ DR_RX_ACTIVE_ID MPH0_DIR_DPPULLUP/ DR_RESET MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 83 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER/GPIO2[26] TSEC1_RXD[7:4]/ B16, D16, E16, F16 GPIO2[22:25] TSEC1_RXD[3:0] E10, A8, F10, B8 TSEC1_TX_CLK TSEC1_TXD[7:4]/GPIO2[27:30] A15, B15, A14, B14 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 84 TSEC2_TXD[3:0]/GPIO1[17:20] B5, A5, F8, B6 TSEC2_TX_ER/GPIO1[24] TSEC2_TX_EN/GPIO1[12] TSEC2_TX_CLK/GPIO1[30] DUART UART_SOUT[1:2]/ AK27, AN29 MSRCID[0:1]/LSRCID[0:1] UART_SIN[1:2]/ AL28, AM29 MSRCID[2:3]/LSRCID[2:3] UART_CTS[1]/ AP30 MSRCID4/LSRCID4 UART_CTS[2]/ AN30 MDVAL/ LDVAL UART_RTS[1:2] AP31, AM30 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 85 Clocks PCI_CLK_OUT[0:2] AN9, AP9, AM10, PCI_CLK_OUT[3]/LCS[6] AN10 PCI_CLK_OUT[4]/LCS[7] AJ11 PCI_CLK_OUT[5:7] AP10, AL11, AM11 PCI_SYNC_IN/PCI_CLOCK AK12 PCI_SYNC_OUT AP11 RTC/PIT_CLOCK AM32 CLKIN JTAG TRST Test TEST TEST_SEL AL13 QUIESCE MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 86 C9, D11 Power for Three Speed Ethernet #1 and for Ethernet Management Interface I/O (2.5V, 3.3V) C6, D9 Power for Three Speed Ethernet #2 I/O (2.5V, 3.3V) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 87 9. It is recommended that MDIC0 be tied to GRD using an 18 Ω resistor and MDIC1 be tied to DDR power using an 18 Ω resistor. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 88: Clocking

    PCI agent devices in the system, to allow the MPC8349EA to function. When the MPC8349EA is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal should be tied to GND. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 89 TSEC2, I Off, csb_clk csb_clk csb_clk Security Core Off, , csb_clk/2, csb_clk csb_clk USB DR, USB MPH Off, csb_clk, csb_clk/2, csb_clk PCI1, PCI2 and DMA complex csb_clk Off, MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 90 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the ccb_clk frequency (depending on RCWL[LBIUCM]). MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 91 (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 58 Table 59 show the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 92 8 : 1 CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 93 RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 60 shows the encodings for RCWL[COREPLL]. COREPLL values that are not listed in Table 60 should be considered as reserved. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 94 Core VCO frequency = Core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency is in the range of 800–1800 MHz. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 95 66 MHz CLKIN/PCI_CLK Options 0011 0000100 0011 0100100 0100 0000011 0100 0100011 0011 0000101 — 0100 0000100 — 0011 0000100 — — 0100 0000101 — — 0101 0000100 — — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 96 The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4–15 associated with the SPMF and COREPLL settings given in the table. The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 97: Thermal

    For the following sections, P = (V ) + P where P is the power dissipation of the I/O drivers. Table 5 for I/O power dissipation values. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 98 When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 99 The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 100 Alpha Novatech 408-567-8082 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 818-842-7277 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 101 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces, and its performance should be verified under the application requirements. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 102 + (R θ where: = junction temperature (°C) = case temperature of the package (°C) = junction to case thermal resistance (°C/W) θ = power dissipation (W) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 103: System Design Information

    PLL power supply filter circuit. 10 Ω (or L2AV 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors Figure 40. PLL Power Supply Filter Circuit MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 104 /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each other in value. Then, Z = (R )/2. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 105 PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 106 1 (as with an IC). Regardless of the numbering scheme, the signal placement recommended in Figure 42 is common to all known emulators. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 107 COP header. The resistor value for VDD_SENSE should be around 20Ω . 2. Key location; pin 14 is not physically present on the COP header. Figure 42. JTAG Interface Connection MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 108 System Design Information MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...

  • Page 109: Document Revision History

    Freescale sales office. Also the part numbering scheme includes an application modifier to specify special application conditions. Each part number also contains a revision code that refers to the die mask revision number. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 110 ATWLYYWW is the traceability code. CCCCC is the country code. MMMMM is the mask number. YWWLAZ is the assembly traceability code. Figure 43. Freescale Part Marking for TBGA Devices MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 111 Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor...
  • Page 112 1-8-1, Shimo-Meguro, Meguro-ku surgical implant into the body, or other applications intended to support or sustain life, Tokyo 153-0064, Japan or for any other application in which the failure of the Freescale Semiconductor product 0120 191014 +81 3 5437 9125 could create a situation where personal injury or death may occur.

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