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Manuals and User Guides for Freescale Semiconductor DSP56366. We have
1
Freescale Semiconductor DSP56366 manual available for free PDF download: User Manual
Freescale Semiconductor DSP56366 User Manual (366 pages)
24-Bit Digital Signal Processor
Brand:
Freescale Semiconductor
| Category:
Computer Hardware
| Size: 3 MB
Table of Contents
Table of Contents
3
Manual Conventions
22
1 DSP56366 Overview
25
Introduction
25
Figure 1-1 DSP56366 Block Diagram
25
DSP56300 Core Description
26
DSP56366 Audio Processor Architecture
27
DSP56300 Core Functional Blocks
27
Data ALU
28
Data ALU Registers
28
Multiplier-Accumulator (MAC)
28
Address Generation Unit (AGU)
29
Program Control Unit (PCU)
29
Internal Buses
30
Direct Memory Access (DMA)
30
PLL-Based Clock Oscillator
31
JTAG TAP and Once Module
31
On-Chip Memory
31
Off-Chip Memory Expansion
32
Peripheral Overview
32
Host Interface (HDI08)
33
General Purpose Input/Output (GPIO)
33
Triple Timer (TEC)
33
Enhanced Serial Audio Interface (ESAI)
34
Enhanced Serial Audio Interface 1 (ESAI_1)
34
Serial Host Interface (SHI)
34
Digital Audio Transmitter (DAX)
34
2 Signal/Connection Descriptions
35
Signal Groupings
35
Table 2-1 DSP56364 Functional Signal Groupings
35
Figure 2-1 Signals Identified by Functional Group
36
Power
37
Ground
37
Table 2-2 Power Inputs
37
Table 2-3 Grounds
37
Clock and PLL
38
Table 2-4 Clock and PLL Signals
38
External Memory Expansion Port (Port A)
39
External Address Bus
39
External Data Bus
39
External Bus Control
39
Table 2-5 External Address Bus Signals
39
Table 2-6 External Data Bus Signals
39
Table 2-7 External Bus Control Signals
39
Interrupt and Mode Control
41
Table 2-8 Interrupt and Mode Control
42
Parallel Host Interface (Hdi08)
43
Table 2-9 Host Interface
43
Serial Host Interface
46
Table 2-10 Serial Host Interface Signals
46
Enhanced Serial Audio Interface
49
Table 2-11 Enhanced Serial Audio Interface Signals
49
Enhanced Serial Audio Interface_1
53
Table 2-12 Enhanced Serial Audio Interface_1 Signals
53
SPDIF Transmitter Digital Audio Interface
55
Table 2-13 Digital Audio Interface (DAX) Signals
55
Timer
56
Jtag/Once Interface
56
Table 2-14 Timer Signal
56
Table 2-15 Jtag/Once Interface
56
3 Memory Configuration
57
Data and Program Memory Maps
57
Table 3-1 Internal Memory Configurations
57
Table 3-2 On-Chip RAM Memory Locations
58
Table 3-3 On-Chip ROM Memory Locations
58
Figure 3-1 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=0
59
Figure 3-2 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=0
59
Figure 3-3 Memory Maps for MSW=(0,0), CE=0 MS=1, SC=0
60
Figure 3-4 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=0
60
Figure 3-5 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=0
61
Figure 3-6 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=0
61
Figure 3-7 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=0
62
Figure 3-8 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=0
62
Figure 3-10 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=1
63
Figure 3-9 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=1
63
Figure 3-11 Memory Maps for MSW=(0,0), CE=0, MS=1, SC=1
64
Figure 3-12 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=1
64
Figure 3-13 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=1
65
Figure 3-14 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=1
65
Figure 3-15 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=1
66
Figure 3-16 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=1
66
Dynamic Memory Configuration Switching
67
Reserved Memory Spaces
67
Bootstrap ROM
67
External Memory Support
68
Table 3-4 Internal I/O Memory Map
68
Introduction
75
Operating Mode Register (OMR)
75
4 Core Configuration
75
Asynchronous Bus Arbitration Enable (ABE) - Bit 13
76
Address Attribute Priority Disable (APD) - Bit 14
76
Address Tracing Enable (ATE) - Bit 15
76
Patch Enable (PEN) - Bit 23
76
Table 4-1 Operating Mode Register (OMR)
76
Table 4-2 DSP56366 Operating Modes
78
Table 4-3 DSP56366 Mode Descriptions
79
Interrupt Priority Registers
80
Table 4-4 Interrupt Priority Level Bits
80
Figure 4-1 Interrupt Priority Register P
81
Figure 4-2 Interrupt Priority Register C
81
Table 4-5 Interrupt Sources Priorities Within an IPL
82
Table 4-6 DSP56366 Interrupt Vectors
84
Table 4-7 DMA Request Sources
86
PLL Multiplication Factor (MF0-MF11)
87
Device Identification (ID) Register
87
JTAG Identification (ID) Register
87
PLL Pre-Divider Factor (PD0-PD3)
87
Crystal Range Bit (XTLR)
87
XTAL Disable Bit (XTLD)
87
PLL Initialization
87
Table 4-8 Identification Register Configuration
87
JTAG Boundary Scan Register (BSR)
88
Table 4-9 JTAG Identification Register Configuration
88
Table 4-10 DSP56366 BSR Bit Definition
88
Introduction
93
5 General Purpose Input/Output
93
Port B Signals and Registers
93
Port C Signals and Registers
93
Port D Signals and Registers
93
Programming Model
93
Port E Signals and Registers
94
Timer/Event Counter Signals
94
6 Host Interface (HDI08)
95
Interface - DSP Side
95
HDI08 Features
95
Introduction
95
Interface - Host Side
96
HDI08 Host Port Signals
97
Table 6-1 HDI08 Signal Summary
97
HDI08 Block Diagram
98
Table 6-2 Strobe Signals Support Signals
98
Table 6-3 Host Request Support Signals
98
HDI08 – DSP-Side Programmer's Model
99
Figure 6-1 HDI08 Block Diagram
99
Host Transmit Data Register (HOTX)
100
Host Receive Data Register (HORX)
100
HCR Host Transmit Interrupt Enable (HTIE) Bit 1
101
HCR Host Receive Interrupt Enable (HRIE) Bit 0
101
HCR Host Command Interrupt Enable (HCIE) Bit 2
101
Host Control Register (HCR)
101
Figure 6-2 Host Control Register (HCR) (X:$FFFFC2)
101
HCR Host DMA Mode Control Bits (HDM0, HDM1, HDM2) Bits 5-7
102
HCR Host Flags 2,3 (HF2,HF3) Bits 3-4
102
Table 6-4 HDI08 IRQ
102
Table 6-5 HDM[2:0] Functionality
102
HSR Host Transmit Data Empty (HTDE) Bit 1
104
HSR Host Receive Data Full (HRDF) Bit 0
104
HSR Host Command Pending (HCP) Bit 2
104
HCR Reserved Bits 8-15
104
Host Status Register (HSR)
104
Figure 6-3 Host Status Register (HSR) (X:FFFFC3)
104
HSR Host Flags 0,1 (HF0,HF1) Bits 3-4
105
HBAR Base Address (BA[10:3]) Bits 0-7
105
HSR Reserved Bits 5-6, 8-15
105
HSR DMA Status (DMA) Bit 7
105
Host Base Address Register (HBAR)
105
Figure 6-4 Host Base Address Register (HBAR) (X:$FFFFC5)
105
HPCR Host GPIO Port Enable (HGEN) Bit 0
106
HBAR Reserved Bits 8-15
106
Host Port Control Register (HPCR)
106
Figure 6-5 Self Chip Select Logic
106
Figure 6-6 Host Port Control Register (HPCR) (X:$FFFFC4)
106
HPCR Host Address Line 8 Enable (HA8EN) Bit 1
107
HPCR Host Address Line 9 Enable (HA9EN) Bit 2
107
HPCR Host Chip Select Enable (HCSEN) Bit 3
107
HPCR Host Acknowledge Enable (HAEN) Bit 5
107
HPCR Host Request Enable (HREN) Bit 4
107
HPCR Host Enable (HEN) Bit 6
107
HPCR Reserved Bit 7
107
HPCR Host Address Strobe Polarity (HASP) Bit 10
108
HPCR Host Data Strobe Polarity (HDSP) Bit 9
108
HPCR Host Request Open Drain (HROD) Bit 8
108
HPCR Host Multiplexed Bus (HMUX) Bit 11
108
HPCR Host Dual Data Strobe (HDDS) Bit 12
108
Figure 6-7 Single Strobe Bus
108
HPCR Host Chip Select Polarity (HCSP) Bit 13
109
HPCR Host Acknowledge Polarity (HAP) Bit 15
109
HPCR Host Request Polarity (HRP) Bit 14
109
Data Direction Register (HDDR)
109
Figure 6-8 Dual Strobes Bus
109
DSP-Side Registers after Reset
110
Host Data Register (HDR)
110
Figure 6-9 Host Data Direction Register (HDDR) (X:$FFFFC8)
110
Figure 6-10 Host Data Register (HDR) (X:$FFFFC9)
110
Table 6-6 HDR and HDDR Functionality
110
Host Interface DSP Core Interrupts
111
Table 6-7 DSP-Side Registers after Reset
111
HDI08 – External Host Programmer's Model
112
Figure 6-11 HSR-HCR Operation
112
Interface Control Register (ICR)
113
Table 6-8 HDI08 Host Side Register Map
113
Figure 6-12 Interface Control Register (ICR)
114
ICR Receive Request Enable (RREQ) Bit 0
114
ICR Transmit Request Enable (TREQ) Bit 1
114
ICR Double Host Request (HDRQ) Bit 2
115
ICR Host Flag 0 (HF0) Bit 3
115
ICR Host Flag 1 (HF1) Bit 4
115
Table 6-9 TREQ RREQ Interrupt Mode (HDM[2:0]=000 or HM[1:0]=00)
115
ICR Host Little Endian (HLEND) Bit 5
116
Table 6-12 Host Mode Bit Definition
116
Command Vector Register (CVR)
117
CVR Host Vector (HV[6:0]) Bits 0–6
117
Figure 6-13 Command Vector Register (CVR)
117
ICR Initialize Bit (INIT) Bit 7
117
Table 6-13 INIT Command Effect
117
CVR Host Command Bit (HC) Bit 7
118
Figure 6-14 Interface Status Register (ISR)
118
Interface Status Register (ISR)
118
ISR Receive Data Register Full (RXDF) Bit 0
118
ISR Transmit Data Register Empty (TXDE) Bit 1
118
ISR Host Flag 2 (HF2) Bit 3
119
ISR Host Flag 3 (HF3) Bit 4
119
ISR Host Request (HREQ) Bit 7
119
ISR Reserved Bits 5-6
119
ISR Transmitter Ready (TRDY) Bit 2
119
Table 6-14 Host Request Status (HREQ)
119
Transmit Byte Registers (TXH:TXM:TXL)
120
Receive Byte Registers (RXH:RXM:RXL)
120
Interrupt Vector Register (IVR)
120
Figure 6-15 Interrupt Vector Register (IVR)
120
General Purpose INPUT/OUTPUT (GPIO)
121
Table 6-15 Host Side Registers after Reset
121
HDI08 Host Processor Data Transfer
122
Servicing the Host Interface
122
Polling
122
Servicing Interrupts
123
Figure 6-16 HDI08 Host Request Structure
123
Introduction
125
Serial Host Interface
125
7 Serial Host Interface
126
SHI Clock Generator
126
Serial Host Interface Internal Architecture
126
Figure 7-1 Serial Host Interface Block Diagram
126
Serial Host Interface Programming Model
127
Figure 7-2 SHI Clock Generator
127
Figure 7-3 SHI Programming Model-Host Side
127
Figure 7-4 SHI Programming Model-DSP Side
128
SHI Input/Output Shift Register (Iosr)—Host Side
129
Table 7-1 SHI Interrupt Vectors
129
Table 7-2 SHI Internal Interrupt Priorities
129
Figure 7-5 SHI I/O Shift Register (IOSR)
130
Clock Phase and Polarity (CPHA and Cpol)—Bits 1–0
131
HSAR Reserved Bits—Bits 19, 17–0
131
SHI Clock Control Register (HCKR)—DSP Side
131
Figure 7-6 SPI Data-To-Clock Timing Diagram
132
HCKR Divider Modulus Select (Hdm[7:0])—Bits 10–3
133
HCKR Filter Mode (HFM[1:0]) — Bits 13–12
133
HCKR Prescaler Rate Select (Hrs)—Bit 2
133
HCKR Reserved Bits—Bits 23–14, 11
133
HCSR Host Enable (Hen)—Bit 0
134
SHI Control/Status Register (HCSR)—DSP Side
134
Table 7-3 SHI Noise Reduction Filter Mode
134
HCSR Serial Host Interface Mode (Hm[1:0])—Bits 3–2
135
SHI Individual Reset
135
Table 7-4 SHI Data Size
135
HCSR FIFO-Enable Control (Hfifo)—Bit 5
136
HCSR Host-Request Enable (Hrqe[1:0])—Bits 8–7
136
HCSR Master Mode (Hmst)—Bit 6
136
Table 7-5 HREQ Function in SHI Slave Modes
136
HCSR Bus-Error Interrupt Enable (Hbie)—Bit 10
137
HCSR Idle (Hidle)—Bit 9
137
HCSR Transmit-Interrupt Enable (Htie)—Bit 11
137
HCSR Host Transmit Underrun Error (Htue)—Bit 14
138
HCSR Receive Interrupt Enable (Hrie[1:0])—Bits 13–12
138
Table 7-6 HCSR Receive Interrupt Enable Bits
138
HCSR Host Transmit Data Empty (Htde)—Bit 15
139
HCSR Reserved Bits—Bits 23, 18 and 16
139
Host Receive FIFO Full (Hrff)—Bit 19
139
Host Receive FIFO Not Empty (Hrne)—Bit 17
139
Host Receive Overrun Error (Hroe)—Bit 20
139
HCSR Host Busy (Hbusy)—Bit 22
140
Host Bus Error (Hber)—Bit 21
140
SHI Host Receive Data FIFO (HRX)—DSP Side
130
SHI Host Transmit Data Register (HTX)—DSP Side
130
SHI Slave Address Register (HSAR)—DSP Side
130
Characteristics of the SPI Bus
140
Characteristics of the I 2 C Bus
140
Overview
141
Figure 7-7 I 2 C Bit Transfer
141
Figure 7-9 Acknowledgment on the I C Bus
142
Figure 7-10 I 2 C Bus Protocol for Host Write Cycle
142
SHI Programming Considerations
143
SPI Slave Mode
143
Figure 7-11 I 2 C Bus Protocol for Host Read Cycle
143
SPI Master Mode
144
I 2 C Slave Mode
145
Slave Mode
146
I 2 C Master Mode
147
Master Mode
148
SHI Operation During DSP Stop
149
Enhanced Serial AUDIO Interface (ESAI)
151
Introduction
151
Figure 8-1 ESAI Block Diagram
152
8 Enhanced Serial AUDIO Interface (ESAI)
153
Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3)
153
Serial Transmit 0 Data Pin (SDO0)
153
Serial Transmit 1 Data Pin (SDO1)
153
ESAI Data and Control Pins
153
Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2)
154
Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1)
154
Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0)
154
Receiver Serial Clock (SCKR)
154
Table 8-1 Receiver Clock Sources (Asynchronous Mode Only)
155
Transmitter Serial Clock (SCKT)
155
Frame Sync for Receiver (FSR)
156
Table 8-2 Transmitter Clock Sources
156
ESAI Programming Model
157
Frame Sync for Transmitter (FST)
157
High Frequency Clock for Receiver (HCKR)
157
High Frequency Clock for Transmitter (HCKT)
157
ESAI Transmitter Clock Control Register (TCCR)
158
Figure 8-2 TCCR Register
158
TCCR Transmit Prescale Modulus Select (TPM7–TPM0) - Bits 0–7
158
Figure 8-3 ESAI Clock Generator Functional Block Diagram
159
TCCR Transmit Prescaler Range (TPSR) - Bit 8
159
TCCR Tx Frame Rate Divider Control (TDC4–TDC0) - Bits 9–13
160
Figure 8-4 ESAI Frame Sync Generator Functional Block Diagram
161
Table 8-3 Transmitter High Frequency Clock Divider
161
TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14–17
161
TCCR Transmit Clock Polarity (TCKP) - Bit 18
162
TCCR Transmit Clock Source Direction (TCKD) - Bit 21
162
TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19
162
TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22
162
TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20
162
TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23
162
ESAI Transmit Control Register (TCR)
162
Figure 8-5 TCR Register
163
TCR ESAI Transmit 0 Enable (TE0) - Bit 0
163
TCR ESAI Transmit 1 Enable (TE1) - Bit 1
163
TCR ESAI Transmit 2 Enable (TE2) - Bit 2
164
TCR ESAI Transmit 3 Enable (TE3) - Bit 3
164
TCR ESAI Transmit 4 Enable (TE4) - Bit 4
164
TCR ESAI Transmit 5 Enable (TE5) - Bit 5
165
TCR Transmit Shift Direction (TSHFD) - Bit 6
165
TCR Transmit Word Alignment Control (TWA) - Bit 7
165
Table 8-4 Transmit Network Mode Selection
166
TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-9
166
Figure 8-6 Normal and Network Operation
167
TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-14
168
Table 8-5 ESAI Transmit Slot and Word Length Selection
168
TCR Transmit Frame Sync Length (TFSL) - Bit 15
169
Figure 8-7 Frame Length Selection
170
TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20
171
TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16
171
TCR Transmit Section Personal Reset (TPR) - Bit 19
171
TCR Transmit Zero Padding Control (PADC) - Bit 17
171
TCR Reserved Bit - Bits 18
171
TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21
172
TCR Transmit Interrupt Enable (TIE) - Bit 22
172
TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23
172
ESAI Receive Clock Control Register (RCCR)
172
Figure 8-8 RCCR Register
172
RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0
173
RCCR Receiver Prescaler Range (RPSR) - Bit 8
173
RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 9–13
173
RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17
173
RCCR Receiver Clock Polarity (RCKP) - Bit 18
174
RCCR Receiver Clock Source Direction (RCKD) - Bit 21
174
RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19
174
RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20
174
Table 8-6 Receiver High Frequency Clock Divider
174
RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22
175
Table 8-7 SCKR Pin Definition Table
175
Table 8-8 FSR Pin Definition Table
175
RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23
176
ESAI Receive Control Register (RCR)
176
Figure 8-9 RCR Register
176
Table 8-9 HCKR Pin Definition Table
176
RCR ESAI Receiver 0 Enable (RE0) - Bit 0
177
RCR ESAI Receiver 1 Enable (RE1) - Bit 1
177
RCR ESAI Receiver 2 Enable (RE2) - Bit 2
177
RCR ESAI Receiver 3 Enable (RE3) - Bit 3
177
RCR Receiver Shift Direction (RSHFD) - Bit 6
177
RCR Reserved Bits - Bits 4-5, 17-18
177
RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-9
178
RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14
178
RCR Receiver Word Alignment Control (RWA) - Bit 7
178
Table 8-10 ESAI Receive Network Mode Selection
178
Table 8-11 ESAI Receive Slot and Word Length Selection
179
RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16
180
RCR Receiver Section Personal Reset (RPR) - Bit 19
180
RCR Receiver Frame Sync Length (RFSL) - Bit 15
180
RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21
181
RCR Receive Exception Interrupt Enable (REIE) - Bit 20
181
RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23
181
RCR Receive Interrupt Enable (RIE) - Bit 22
181
ESAI Common Control Register (SAICR)
181
SAICR Synchronous Mode Selection (SYN) - Bit 6
182
SAICR Serial Output Flag 0 (OF0) - Bit 0
182
SAICR Serial Output Flag 1 (OF1) - Bit 1
182
SAICR Serial Output Flag 2 (OF2) - Bit 2
182
SAICR Reserved Bits - Bits 3-5, 9-23
182
Figure 8-10 SAICR Register
182
SAICR Transmit External Buffer Enable (TEBE) - Bit 7
183
SAICR Alignment Control (ALC) - Bit 8
183
ESAI Status Register (SAISR)
184
Figure 8-11 SAICR SYN Bit Operation
184
Figure 8-12 SAISR Register
185
SAISR Receive Frame Sync Flag (RFS) - Bit 6
185
SAISR Reserved Bits - Bits 3-5, 11-12, 18-23
185
SAISR Serial Input Flag 0 (IF0) - Bit 0
185
SAISR Serial Input Flag 1 (IF1) - Bit 1
185
SAISR Serial Input Flag 2 (IF2) - Bit 2
185
SAISR Receive Data Register Full (RDF) - Bit 8
186
SAISR Receive Even-Data Register Full (REDF) - Bit 9
186
SAISR Receive Odd-Data Register Full (RODF) - Bit 10
186
SAISR Receiver Overrun Error Flag (ROE) - Bit 7
186
SAISR Transmit Frame Sync Flag (TFS) - Bit 13
186
SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16
187
SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17
187
SAISR Transmit Underrun Error Flag (TUE) - Bit 14
187
SAISR Transmit Data Register Empty (TDE) - Bit 15
187
Figure 8-13 ESAI Data Path Programming Model ([R/T]SHFD=0)
188
Figure 8-14 ESAI Data Path Programming Model ([R/T]SHFD=1)
189
ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0)
190
ESAI Receive Data Registers (RX3, RX2, RX1, RX0)
190
ESAI Transmit Shift Registers
190
ESAI Receive Shift Registers
190
Transmit Slot Mask Registers (TSMA, TSMB)
190
ESAI Time Slot Register (TSR)
190
Figure 8-15 TSMA Register
191
Figure 8-16 TSMB Register
191
Receive Slot Mask Registers (RSMA, RSMB)
192
Figure 8-17 RSMA Register
192
Figure 8-18 RSMB Register
192
Operating Modes
193
ESAI Initialization
193
ESAI after Reset
193
ESAI Interrupt Requests
194
Normal/Network/On-Demand Mode Selection
195
Operating Modes – Normal, Network, and On-Demand
195
Synchronous/Asynchronous Operating Modes
195
Frame Sync Selection
196
Shift Direction Selection
196
Serial I/O Flags
196
GPIO - Pins and Registers
197
Port C Direction Register (PRRC)
197
Port C Control Register (PCRC)
197
Port C Data Register (PDRC)
198
Figure 8-19 PCRC Register
198
Figure 8-20 PRRC Register
198
Table 8-12 PCRC and PRRC Bits Functionality
198
Initializing Just the ESAI Transmitter Section
199
Initializing the ESAI Using Individual Reset
199
ESAI Initialization Examples
199
Figure 8-21 PDRC Register
199
Initializing Just the ESAI Receiver Section
200
Enhanced Serial Audio Interface 1 (ESAI_1)
201
Introduction
201
Figure 9-1 ESAI_1 Block Diagram
202
9 Enhanced Serial Audio Interface 1 (ESAI_1)
203
Serial Transmit 2/Receive 3 Data Pin (SDO2_1/SDI3_1)
203
Serial Transmit 3/Receive 2 Data Pin (SDO3_1/SDI2_1)
203
Serial Transmit 4/Receive 1 Data Pin (SDO4_1/SDI1_1)
203
Serial Transmit 0 Data Pin (SDO0_1)
203
Serial Transmit 1 Data Pin (SDO1_1)
203
ESAI_1 Data and Control Pins
203
Serial Transmit 5/Receive 0 Data Pin (SDO5_1/SDI0_1)
204
Transmitter Serial Clock (SCKT_1)
204
Frame Sync for Transmitter (FST_1)
204
Receiver Serial Clock (SCKR_1)
204
Frame Sync for Receiver (FSR_1)
204
ESAI_1 Programming Model
204
ESAI_1 Transmitter Clock Control Register (TCCR_1)
205
ESAI_1 Multiplex Control Register (EMUXR)
205
Figure 9-2 EMUXR Register
205
Table 9-1 EMUXR ESA/ESAI_1 Pin Selection
205
Figure 9-3 TCCR_1 Register
206
Table 9-2 Transmitter Clock Sources
206
TCCR_1 Tx High Freq. Clock Direction (THCKD) - Bit 23
206
TCCR_1 Tx High Freq. Clock Divider (TFP3-TFP0) - Bits 14–17
206
TCCR_1 Tx High Freq. Clock Polarity (THCKP) - Bit 20
206
Figure 9-4 ESAI_1 Clock Generator Functional Block Diagram
207
Figure 9-6 TCR_1 Register
208
ESAI_1 Transmit Control Register (TCR_1)
208
Figure 9-5 ESAI_1 Frame Sync Generator Functional Block Diagram
208
Figure 9-7 RCCR_1 Register
209
RCCR_1 Rx High Freq. Clock Divider (RFP3-RFP0) - Bits 14–17
209
RCCR_1 Rx High Freq. Clock Polarity (RHCKP) - Bit 20
209
ESAI_1 Receive Clock Control Register (RCCR_1)
209
RCCR_1 Rx High Freq. Clock Direction (RHCKD) - Bit 23
209
Table 9-3 Receiver Clock Sources (Asynchronous Mode Only)
209
Figure 9-8 RCR_1 Register
210
Figure 9-9 SAICR_1 Register
210
ESAI_1 Common Control Register (SAICR_1)
210
ESAI_1 Receive Control Register (RCR_1)
210
ESAI_1 Status Register (SAISR_1)
210
Figure 9-10 SAISR_1 Register
211
ESAI_1 Transmit Shift Registers
211
ESAI_1 Receive Shift Registers
211
ESAI_1 Transmit Data Registers
211
ESAI_1 Receive Data Registers
211
Figure 9-11 TSMA_1 Register
212
Figure 9-12 TSMB_1 Register
212
Transmit Slot Mask Registers (TSMA_1, TSMB_1)
212
Receive Slot Mask Registers (RSMA_1, RSMB_1)
212
ESAI_1 Time Slot Register (TSR_1)
212
Figure 9-13 RSMA_1 Register
213
Figure 9-14 RSMB_1 Register
213
Operating Modes
213
Port E Control Register (PCRE)
213
GPIO - Pins and Registers
213
ESAI_1 after Reset
213
Port E Direction Register (PRRE)
214
Port E Data Register (PDRE)
214
Figure 9-15 PCRE Register
214
Figure 9-16 PRRE Register
214
Table 9-4 PCRE and PRRE Bits Functionality
214
Figure 9-17 PDRE Register
215
Introduction
217
10 Digital Audio Transmitter
217
DAX Functional Overview
218
DAX Signals
218
Figure 10-1 Digital Audio Transmitter (DAX) Block Diagram
218
DAX Programming Model
219
DAX Internal Architecture
220
Figure 10-2 DAX Programming Model
220
Table 10-1 DAX Interrupt Vectors
220
Table 10-2 DAX Interrupt Priority
220
DAX Channel a Validity (Xva)—Bit 10
221
DAX Audio Data Buffers (XADBUFA / XADBUFB)
221
DAX Audio Data Shift Register (XADSR)
221
DAX Non-Audio Data Register (XNADR)
221
DAX Audio Data Register (XADR)
221
DAX Channel a Channel Status (Xca)—Bit 12
222
DAX Channel B Channel Status (Xcb)—Bit 15
222
DAX Channel a User Data (Xua)—Bit 11
222
DAX Channel B Validity (Xvb)—Bit 13
222
DAX Channel B User Data (Xub)—Bit 14
222
XNADR Reserved Bits—Bits 0-9, 16–23
222
DAX Non-Audio Data Buffer (XNADBUF)
222
DAX Control Register (XCTR)
222
Audio Data Register Empty Interrupt Enable (Xdie)—Bit 0
223
Block Transferred Interrupt Enable (Xbie)—Bit 2
223
Underrun Error Interrupt Enable (Xuie)—Bit 1
223
DAX Clock Input Select (Xcs[1:0])—Bits 3–4
223
XCTR Reserved Bits—Bits 6-23
223
DAX Start Block (Xsb)—Bit 5
223
DAX Status Register (XSTR)
223
Table 10-3 Clock Source Selection
223
DAX Audio Data Register Empty (Xade)—Bit 0
224
DAX Block Transfer Flag (Xblk)—Bit 2
224
DAX Transmit Underrun Error Flag (Xaur)—Bit 1
224
XSTR Reserved Bits—Bits 3–23
224
Figure 10-3 DAX Relative Timing
224
DAX Parity Generator (PRTYG)
225
DAX Preamble Generator
225
DAX Clock Multiplexer
225
DAX Biphase Encoder
225
Figure 10-4 Preamble Sequence
225
Table 10-4 Preamble Bit Patterns
225
Audio Data Register Empty Interrupt Handling
226
DAX Programming Considerations
226
Initiating a Transmit Session
226
DAX State Machine
226
Figure 10-5 Clock Multiplexer Diagram
226
Block Transferred Interrupt Handling
227
DAX Operation with DMA
227
Table 10-5 Examples of DMA Configuration
227
GPIO (PORT D) - Pins and Registers
228
Port D Control Register (PCRD)
228
DAX Operation During Stop
228
Figure 10-6 Examples of Data Organization in Memory
228
Port D Direction Register (PRRD)
229
Figure 10-7 Port D Direction Register (PRRD)
229
Table 10-6 DAX Port GPIO Control Register Functionality
229
Port D Data Register (PDRD)
230
Figure 10-8 Port D Data Register (PDRD)
230
11 Timer/ Event Counter
231
Introduction
231
Timer/Event Counter Architecture
231
Timer/Event Counter Block Diagram
231
Individual Timer Block Diagram
232
Figure 11-1 Timer/Event Counter Block Diagram
232
Timer/Event Counter Programming Model
233
Figure 11-2 Timer Block Diagram
233
Figure 11-3 Timer Module Programmer's Model
234
TPLR Prescaler Preload Value PL[20:0] Bits 20–0
235
TPLR Prescaler Source PS[1:0] Bits 22-21
235
Prescaler Counter
235
Timer Prescaler Load Register (TPLR)
235
Figure 11-4 Timer Prescaler Load Register (TPLR)
235
TPCR Prescaler Counter Value PC[20:0] Bits 20–0
236
TPCR Reserved Bits 23–21
236
Timer Control/Status Register (TCSR)
236
TCSR Timer Enable (TE) Bit 0
236
TPLR Reserved Bit 23
236
Timer Prescaler Count Register (TPCR)
236
Figure 11-5 Time Prescaler Count Register (TPCR)
236
Table 11-1 Prescaler Source Selection
236
TCSR Timer Control (TC[3:0]) Bits 4–7
237
TCSR Timer Overflow Interrupt Enable (TOIE) Bit 1
237
TCSR Timer Compare Interrupt Enable (TCIE) Bit 2
237
Table 11-3 Timer Control Bits for Timers 1 and 2
238
Table 11-2 Timer Control Bits for Timer 0
238
TCSR Inverter (INV) Bit 8
239
Table 11-4 Inverter (INV) Bit Operation
239
TCSR Timer Reload Mode (TRM) Bit 9
240
TCSR Direction (DIR) Bit 11
240
TCSR Data Output (DO) Bit 13
240
TCSR Data Input (DI) Bit 12
240
TCSR Prescaler Clock Enable (PCE) Bit 15
241
TCSR Timer Overflow Flag (TOF) Bit 20
241
TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23)
241
TCSR Timer Compare Flag (TCF) Bit 21
241
Timer Compare Register (TCPR)
242
Timer Count Register (TCR)
242
Timer Modes of Operation
242
Timer Load Register (TLR)
242
Timer GPIO (Mode 0)
243
Timer Modes
243
Timer Toggle (Mode 2)
244
Timer Pulse (Mode 1)
244
Timer Event Counter (Mode 3)
245
Measurement Input Width (Mode 4)
246
Signal Measurement Modes
246
Measurement Accuracy
246
Measurement Input Period (Mode 5)
247
Measurement Capture (Mode 6)
247
Pulse Width Modulation (PWM, Mode 7)
248
Watchdog Pulse (Mode 9)
249
Watchdog Modes
249
Timer Behavior During Wait
250
Watchdog Toggle (Mode 10)
250
Reserved Modes
250
Special Cases
250
Timer Behavior During Stop
251
DMA Trigger
251
Appendix A Bootstrap ROM Contents
253
A.1 DSP56366 Bootstrap Program
253
Appendix B Equates
267
Appendix C JTAG BSDL
301
Appendix D Programmer's Reference
309
Table D-1 Internal I/O Memory Map
310
Interrupt Vector Addresses
316
Table D-2 DSP56366 Interrupt Vectors
316
Interrupt Source Priorities (Within an IPL)
318
Table D-3 Interrupt Sources Priorities Within an IPL
318
Table D-4 HDI08 Programming Model
320
Programming Sheets
323
Figure D-1 Status Register (SR
324
Figure D-2 Operating Mode Register (OMR
325
Figure D-3 Interrupt Priority Register-Core (IPR-C
326
Figure D-4 Interrupt Priority Register - Peripherals (IPR-P
327
Figure D-5 Phase Lock Loop Control Register (PCTL
328
Figure D-6 Host Receive and Host Transmit Data Registers
329
Figure D-7 Host Control and Status Registers
330
Figure D-8 Host Base Address and Host Port Control
331
Table 6-11 HDRQ
331
Figure D-9 Host Interrupt Control and Interrupt Status
332
Figure D-10 Host Interrupt Vector and Command Vector
333
Figure D-11 Host Receive and Transmit Byte Registers
334
Figure D-12 SHI Slave Address and Clock Control Registers
335
Figure D-13 SHI Transmit and Receive Data Registers
336
Figure D-14 SHI Host Control/Status Register
337
Figure D-15 ESAI Transmit Clock Control Register
338
Figure D-16 ESAI Transmit Control Register
339
Figure D-17 ESAI Receive Clock Control Register
340
Figure D-18 ESAI Receive Control Register
341
Figure D-19 ESAI Common Control Register
342
Figure D-20 ESAI Status Register
343
Figure D-21 ESAI_1 Multiplex Control Register
344
Figure D-22 ESAI_1 Transmit Clock Control Register
345
Figure D-23 ESAI_1 Transmit Control Register
346
Figure D-24 ESAI_1 Receive Clock Control Register
347
Figure D-25 ESAI_1 Receive Control Register
348
Figure D-26 ESAI_1 Common Control Register
349
Figure D-27 ESAI_1 Status Register
350
Figure D-28 DAX Non-Audio Data Register
351
Figure D-29 DAX Control and Status Registers
352
Figure D-30 Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR
353
Figure D-31 Timer Control/Status Register
354
Figure D-32 Timer Load, Compare and Count Registers
355
Figure D-33 GPIO Port B
356
Figure D-34 GPIO Port C
357
Figure D-35 GPIO Port D
358
Figure D-36 GPIO Port E
359
DSP56366 24-Bit Digital Signal Processor, Rev
361
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