Transfer Error Status Register (Tesr) - Freescale Semiconductor MPC850 User Manual

Table 10-4. SYPCR Field Descriptions (Continued)
Bits Name
30 SWRI Software watchdog reset/interrupt select.
0 The software watchdog timer causes an NMI (system reset interrupt) to the core.
1 The software watchdog timer causes an HRESET. (default)
31 SWP Software watchdog prescale.
0 The software watchdog timer is not prescaled.
1 The software watchdog timer is prescaled by a factor of 2,048. (default)

10.4.4 Transfer Error Status Register (TESR)

The transfer error status register (TESR) has a bit for each transfer error exception source.
Set bits indicate what type of transfer error exception that occurred since bits were last
cleared. Bits are cleared by reset or by writing ones to them. Canceled speculative accesses
that do not cause an interrupt may set these bits. TESR has two identical sets of fields, one
for instruction transfers and one for data transfers.
Bit 0 1 2
Field
Reset
R/W
SPR
Bit 16 17 18
Field — IEXT ITMT IPB0 IPB1 IPB2 IPB3
Reset
R/W
SPR
Figure 10-5. Transfer Error Status Register (TESR)
Table 10-5 describes TESR fields.
Bits Name
0–17 — Reserved, should be cleared.
18 IEXT Instruction external transfer error acknowledge. Set if the cycle is terminated by an externally
generated TEA when an instruction fetch is initiated.
19 ITMT Instruction transfer monitor timeout. Set if the cycle is terminated by a bus monitor timeout when
an instruction fetch is initiated.
20–23 IPB[0–3] Instruction parity error on bytes 0–3. Each byte lane has four parity error status bits; one is set for
the byte that had a parity error when an instruction was fetched. Parity check for memory not
controlled by the memory controller is enabled by SIUMCR[PNCS], see Table 10-3.
24–25 — Reserved, should be cleared.
3 4 5 6
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x020
19 20 21 22
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x022
Table 10-5. TESR Field Descriptions
Chapter 10. System Interface Unit
Description
7 8 9 10 11
—
R/W
23 24 25 26 27
— DEXT DTMT DPB0 DPB1 DPB2 DPB3
R/W
Description
Programming the SIU
12 13 14 15
28 29 30 31