Freescale Semiconductor MC68HC08KH12 Manuals

Manuals and User Guides for Freescale Semiconductor MC68HC08KH12. We have 1 Freescale Semiconductor MC68HC08KH12 manual available for free PDF download: Datasheet

Freescale Semiconductor MC68HC08KH12 Datasheet

Freescale Semiconductor MC68HC08KH12 Datasheet (262 pages)

Freescale Semiconductor Microcontrollers Data Sheet

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 2 MB

Table of Contents

Table of Contents
3
List of Figures
17
List of Tables
21
Contents
23
Section 1. General Description
23
- Introduction
  24
- Features
  24
- MCU Block Diagram
  26
- MCU Block Diagram
  27
- Pin Assignments
  28
- Quad Flat Pack (QFP) Package
  28
- Power Supply Pins
  29
- Ssa
  29
- DD2 , and
  29
- Dd2 Ss2
  29
- Power Supply Bypassing
  29
- Dda Ssa Dd1 Ss1
  29
- DD2 , and VSS2 )
  29
- Oscillator Pins (OSC1 and OSC2)
  30
- External Reset Pin (RST)
  30
- External Interrupt Pin (IRQ1/VPP )
  30
- USB Data Pins
  30
- (DPLUS0-DPLUS4 and DMINUS0-DMINUS4)
  30
- Voltage Regulator out (REGOUT)
  30
- Port a Input/Output (I/O) Pins (PTA7-PTA0)
  31
- Port B I/O Pins (PTB7-PTB0)
  31
- Port C I/O Pins (PTC4-PTC0)
  31
- Port D I/O Pins (PTD7/KBD7-PTD0/KBD0)
  31
- Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1, PTE1/KBE1/TCH0, PTE0/KBE0/TCLK)
  31
- Port F I/O Pins (PTF7/KBF7-PTF0/KBF0)
  32
- Section 2. Memory Map
  33
- Contents
  33
- Introduction
  33
- Memory Map
  34
- I/O Section
  35
- Control, Status, and Data Registers
  36
- Monitor ROM
  43
- Section 3. Random-Access Memory (RAM)
  45
- Contents
  45
- Introduction
  45
- Functional Description
  45
- Section 4. Read-Only Memory (ROM)
  47
- Contents
  47
- Introduction
  47
- Functional Description
  47
- Section 5. Configuration Register (CONFIG)
  49
- Contents
  49
- Introduction
  49
- Functional Description
  49
- Configuration Register (CONFIG)
  50
- Section 6. Central Processor Unit (CPU)
  51
- Contents
  51
- Introduction
  51
- Features
  52
- CPU Registers
  52
- Accumulator (A)
  53
- CPU Registers
  53
- Index Register (H:X)
  54
- Stack Pointer (SP)
  55
- Program Counter (PC)
  56
- Condition Code Register (CCR)
  57
- Arithmetic/Logic Unit (ALU)
  59
- Section 7. System Integration Module (SIM)
  61
- Contents
  61
- Introduction
  62
- SIM Block Diagram
  63
- SIM I/O Register Summary
  64
- SIM Bus Clock Control and Generation
  65
- Bus Timing
  65
- SIM Clock Signals
  65
- Clock Start-Up from por
  66
- Clocks in Stop Mode and Wait Mode
  66
- Reset and System Initialization
  66
- External Pin Reset
  67
- Active Resets from Internal Sources
  67
- External Reset Timing
  67
- Power-On Reset
  68
- Internal Reset Timing
  68
- Sources of Internal Reset
  68
- Computer Operating Properly (COP) Reset
  69
- POR Recovery
  69
- Illegal Opcode Reset
  70
- Illegal Address Reset
  70
- Universal Serial Bus Reset
  70
- SIM Counter
  71
- SIM Counter During Power-On Reset
  71
- SIM Counter During Stop Mode Recovery
  71
- SIM Counter and Reset States
  71
- Exception Control
  72
- Interrupts
  72
- Interrupt Processing
  73
- Hardware Interrupts
  74
- Interrupt Entry
  74
- Interrupt Recognition Example
  75
- SWI Instruction
  76
- Interrupt Status Registers
  76
- Interrupt Status Register 1
  77
- Interrupt Status Register 1 (INT1)
  77
- Interrupt Status Register 2
  78
- Interrupt Status Register 3
  78
- Interrupt Status Register 2 (INT2)
  78
- Reset
  79
- Break Interrupts
  79
- Status Flag Protection in Break Mode
  79
- Low-Power Modes
  79
- Wait Mode
  80
- Stop Mode
  81
- SIM Registers
  83
- Break Status Register (BSR)
  83
MC68HC(7)08KH12 - Rev
83
- Reset Status Register (RSR)
  84
- Break Flag Control Register (BFCR)
  85
- Section 8. Clock Generator Module (CGM)
  87
- Contents
  87
- Introduction
  88
- Features
  89
- Functional Description
  89
- Crystal Oscillator Circuit
  91
- Phase-Locked Loop Circuit (PLL)
  91
- PLL Circuits
  91
- Acquisition and Tracking Modes
  93
- Manual and Automatic PLL Bandwidth Modes
  93
- Programming the PLL
  94
- Special Programming Exceptions
  95
- Base Clock Selector Circuit
  96
- CGM External Connections
  96
- I/O Signals
  98
- Crystal Amplifier Input Pin (OSC1)
  98
- Crystal Amplifier Output Pin (OSC2)
  98
- External Filter Capacitor Pin (CGMXFC)
  98
- PLL Analog Power Pin (VDDA )
  98
- PLL Analog Ground Pin (VSSA )
  98
- Buffered Crystal Clock Output (CGMVOUT)
  99
- Cgmvsel
  99
- Oscillator Enable Signal (SIMOSCEN)
  99
- Crystal Output Frequency Signal (CGMXCLK)
  99
- CGM Base Clock Output (CGMOUT)
  99
- CGM CPU Interrupt (CGMINT)
  99
- CGM Registers
  100
- PLL Control Register (PCTL)
  102
- PLL Bandwidth Control Register (PBWC)
  104
- PLL Multiplier Select Registers (PMSH:PMSL)
  105
- PLL Reference Divider Select Register (PRDS)
  106
- Interrupts
  107
- Special Modes
  107
- Wait Mode
  107
- CGM During Break Interrupts
  108
- Acquisition/Lock Time Specifications
  108
- Acquisition/Lock Time Definitions
  108
- Parametric Influences on Reaction Time
  109
- Choosing a Filter Capacitor
  111
- Reaction Time Calculation
  111
- Section 9. Universal Serial Bus Module (USB)
  113
- Contents
  113
- Features
  114
- Overview
  115
- I/O Register Description of the HUB Function
  116
- USB HUB Root Port Control Register (HRPCR)
  120
- USB HUB Downstream Port Control Register (HDP1CR-HDP4CR)
  121
- USB SIE Timing Interrupt Register (SIETIR)
  123
- USB SIE Timing Status Register (SIETSR)
  125
- USB HUB Address Register (HADDR)
  127
- USB HUB Interrupt Register 0 (HIR0)
  128
- USB HUB Control Register 0 (HCR0)
  129
- USB HUB Endpoint1 Control & Data Register (HCDR)
  131
- USB HUB Status Register (HSR)
  132
- USB HUB Endpoint 0 Data Registers
  134
- (He0D0-He0D7)
  134
- I/O Register Description of the Embedded Device Function
  134
- USB Embedded Device Address Register (DADDR)
  138
- USB Embedded Device Interrupt Register 0 (DIR0)
  138
- USB Embedded Device Interrupt Register 1 (DIR1)
  140
- USB Embedded Device Control Register 0 (DCR0)
  141
- USB Embedded Device Control Register 1 (DCR1)
  143
- USB Embedded Device Status Register (DSR)
  144
MC68HC(7)08KH12 Rev
144
- USB Embedded Device Control Register 2 (DCR2)
  146
- USB Embedded Device Endpoint 0 Data Registers
  147
- (De0D0-De0D7)
  147
- USB Embedded Device Endpoint 1/2 Data Registers
  148
- (De1D0-De1D7)
  148
- Contents
  149
- Introduction
  149
Section 10. Monitor ROM (MON)
149
- Features
  150
- Functional Description
  150
- Entering Monitor Mode
  152
- Data Format
  154
- Echoing
  154
- Break Signal
  155
- Commands
  155
- Baud Rate
  159
- Contents
  161
Section 11. Timer Interface Module (TIM)
161
- Introduction
  162
- Features
  162
- Functional Description
  163
- TIM Counter Prescaler
  165
- Input Capture
  165
- Output Compare
  165
- Unbuffered Output Compare
  166
- Buffered Output Compare
  166
- Pulse Width Modulation (PWM)
  167
- Unbuffered PWM Signal Generation
  168
- Buffered PWM Signal Generation
  169
- PWM Initialization
  170
- Interrupts
  171
- Wait Mode
  171
- TIM During Break Interrupts
  172
- I/O Signals
  172
- TIM Clock Pin (PTE0/TCLK)
  172
- TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)
  173
- I/O Registers
  173
- TIM Status and Control Register (TSC)
  173
- TIM Counter Registers (TCNTH:TCNTL)
  175
- TIM Counter Modulo Registers (TMODH:TMODL)
  176
- TIM Channel Status and Control Registers (TSC0:TSC1)
  177
- TIM Channel Registers (TCH0H/L-TCH1H/L)
  181
- Contents
  183
Section 12. I/O Ports
183
- Introduction
  184
- Port a
  186
- Port a Data Register (PTA)
  186
- Data Direction Register a (DDRA)
  186
- Port B
  188
- Port B Data Register (PTB)
  188
- Data Direction Register B (DDRB)
  189
- Port C
  190
- Port C Data Register (PTC)
  190
- Data Direction Register C (DDRC)
  191
- Port D
  192
- Port D Data Register (PTD)
  193
- Data Direction Register D (DDRD)
  193
- Port E
  195
- Port E Data Register (PTE)
  195
- Data Direction Register E (DDRE)
  196
- Port-E Optical Interface Enable Register
  198
- Port F
  202
MC68HC(7)08KH12 - Rev
202
- Port F Data Register (PTF)
  202
- Data Direction Register F (DDRF)
  203
- Port Options
  204
- Port Option Control Register (POC)
  204
- Section 13. Computer Operating Properly (COP)
  207
- Introduction
  207
- Functional Description
  208
- I/O Signals
  209
- Cgmxclk
  209
- COPCTL Write
  209
- Power-On Reset
  210
- Internal Reset
  210
- Reset Vector Fetch
  210
- COPD (COP Disable)
  210
- COPRS (COP Rate Select)
  210
- COP Control Register (COPCTL)
  211
- Interrupts
  211
- Monitor Mode
  211
- Low-Power Modes
  212
- Wait Mode
  212
- Stop Mode
  212
- COP Module During Break Mode
  212
- Contents
  213
- Introduction
  213
- Features
  213
Section 14. External Interrupt (Irq)
213
- Functional Description
  214
MC68HC(7)08KH12 - Rev
215
- IRQ1/VPP Pin
  215
- Irq1/V
  215
- PP Pin
  215
- IRQ Module During Break Interrupts
  217
- IRQ Status and Control Register (ISCR)
  217
- Contents
  219
Section 15. Keyboard Interrupt Module (KBI)
219
- Introduction
  220
- Features
  220
- Port-D Keyboard Interrupt Block Diagram
  222
- Port-D Keyboard Interrupt Functional Description
  223
- Port-D Keyboard Initialization
  224
- Port-D Keyboard Interrupt Registers
  225
- Port-D Keyboard Status and Control Register
  225
- Port-D Keyboard Interrupt Enable Register
  226
- Port-E Keyboard Interrupt Block Diagram
  228
- Port-E Keyboard Interrupt Functional Description
  229
- Port-E Keyboard Initialization
  230
- Port-E Keyboard Interrupt Registers
  231
- Port-E Keyboard Status and Control Register
  231
- Port-E Keyboard Interrupt Enable Register
  232
- Port-F Keyboard Interrupt Block Diagram
  234
- Port-F Keyboard Interrupt Functional Description
  235
- Port-F Keyboard Initialization
  236
- Port-F Keyboard Interrupt Registers
  237
- Port-F Keyboard Status and Control Register
  237
- Port-F Keyboard Interrupt Enable Register
  238
- Port-F Pull-Up Enable Register
  239
- Wait Mode
  239
- Stop Mode
  239
- Keyboard Module During Break Interrupts
  239
- Contents
  241
- Introduction
  241
Section 16. Break Module (Break)
241
- Features
  242
- Functional Description
  242
- Flag Protection During Break Interrupts
  244
- CPU During Break Interrupts
  244
- TIM During Break Interrupts
  244
- COP During Break Interrupts
  244
- Break Module Registers
  244
- Break Status and Control Register (BRKSCR)
  245
- Break Address Registers (BRKH and BRKL)
  245
- Low-Power Modes
  246
- Wait Mode
  246
- Stop Mode
  246
- Contents
  247
- Introduction
  247
Section 17. Preliminary Electrical Specifications
247
- Absolute Maximum Ratings
  248
- Functional Operating Range
  249
- Thermal Characteristics
  249
- DC Electrical Characteristics
  250
- Control Timing
  251
- Oscillator Characteristics
  251
- USB DC Electrical Characteristics
  252
- USB Low Speed Source Electrical Characteristics
  253
- USB High Speed Source Electrical Characteristics
  254
- HUB Repeater Electrical Characteristics
  255
- USB Signaling Levels
  256
- Timer Interface Module Characteristics
  256
- Clock Generation Module Characteristics
  257
- CGM Component Specifications
  257
- CGM Electrical Specifications
  257
- Acquisition/Lock Time Specifications
  258
- Contents
  259
- Introduction
  259
Section 18. Mechanical Specifications
259
- Plastic Quad Flat Pack (QFP)
  260

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