Sdram Chip Select Configuration Registers (Csncfg) - Freescale Semiconductor MCF5480 Reference Manual

18.7.2

SDRAM Chip Select Configuration Registers (CSnCFG)

31 30
R
W
Reset 0 0
15 14
R 0 0
W
Reset 0 0
Reg
Addr
Figure 18-9. SRAM Chip Select Configuration Register (CSnCFG)
Bits Name
31–20 CSBA
19–5 —
4–0 CSSZ
Any chip select can be enabled or disabled, independent of others. Any chip select can be allocated any
size of address space from 1 Mbyte to 4 Gbyte, independent of others. Any chip select address space can
begin at any size-aligned base address, independent of others.
For contiguous memory with different sizes of mem banks, place largest bank at lowest address, then place
smaller banks in descending size order at ascending base address.
For example, assume CS0 = 16M, CS1 = empty, CS2 = 64M, CS3 = 64M, CS4 = 256M, CS5 = empty:
CS0CFG = 98000017 = enable 16M @ 0x9800 0000-0x98FF FFFF
CS1CFG = 00000000 = disable
CS2CFG = 90000019 = 64M @ 0x9000 0000-0x93FF FFFF
18-18
29 28 27 26 25
CSBA
0 0 0 0
13 12 11 10
0 0 0 0
0 0 0 0
MBAR + 0x20 (CS0CFG), 0x24 (CS1CFG), 0x28 (CS2CFG), 0x2C (CS3CFG)
Table 18-9. CFnCFG Field Descriptions
Chip select base address.
Reserved. Should be cleared.
Chip select size.
00000 Disabled
00001–10010 Reserved
10011 1 Mbyte, compare A[31:20]
10100 2 Mbyte, compare A[31:21]
10101 4 Mbyte, compare A[31:22]
10110 8 Mbyte, compare A[31:23]
10111 16 Mbyte, compare A[31:24]
11000 32 Mbyte, compare A[31:25]
11001 64 Mbyte, compare A[31:26]
11010 128 Mbyte, compare A[31:27]
11011 256 Mbyte, compare A[31:28]
11100 512 Mbyte, compare A[31:29]
11101 1 Gbyte, compare A[31:30]
11110 2 Gbyte, compare A31
11111 4 Gbyte, ignore A[31:20]
MCF548x Reference Manual, Rev. 3
24 23 22 21
0 0 0 0 0
9 8 7 6 5
0 0 0 0 0
0 0 0 0 0
Description
20 19 18 17
0 0 0
0 0 0 0
4 3 2 1
CSSZ
0 0 0 0
Freescale Semiconductor
16
0
0
0
0