Chip-Select Programming Common To The Gpcm And Upm - Freescale Semiconductor MPC850 User Manual

Chip-Select Programming Common to the GPCM and UPM

multiplexing, address increment, and transfer acknowledge assertion for each memory
access. The UPM specifies a set of signal patterns for a user-specified number of clock
cycles. The UPM RAM pattern run by the memory controller is selected according to the
type of external access transacted. At every clock cycle, the logical value of the external
signals specified in the RAM array is output on the corresponding UPM pins. See Figure
15-4.
Address (A),
Address
Type (AT)
Address
Comparator
Bank Select
MS
Field
Figure 15-4. Basic Memory Controller Operation
15.3 Chip-Select Programming Common to the
GPCM and UPM
The GPCM and the UPMs use the memory controller registers as specified in Table 15-1.
See Section 15.4, "Register Descriptions," for specific register information.
Table 15-1. Memory Controller Register Usage
Base register bank 0–7 register (BRx)
Option register bank 0–7 register (ORx)
Memory status register (MSTAT)
Memory command register (MCR)
Machine A mode register (MAMR)
Machine B mode register (MBMR)
Memory data register (MDR)
Internal/External Memory Access Request Select
UPMA
Signals
Timing
Generator
Register
MPC850 Family User's Manual
UPMB GPCM
Signals
Timing
Generator
MUX
External Signals
Used by the GPCM
√
√
√
Used by a UPM
√
√
√
√
√
√
√