Table of Contents
Advertisement
Field
1
FIFO full.
FFULL
0 The FIFO is not full but may hold up to two unread characters.
1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full are lost.
0
Receiver ready.
RXRDY
0 The CPU has read the receive buffer and no characters remain in the FIFO after this read.
1 One or more characters were received and are waiting in the receive buffer FIFO.
24.3.4
UART Clock Select Registers (UCSRn)
The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal bus
clock as the clocking source for the transmitter and receiver. See
Clock
Source." The transmitter and receiver can use different clock sources. To use the internal bus clock
for both, set UCSRn to 0xDD.
IPSBAR
0x00_0204 (UCSR0)
Offset:
0x00_0244 (UCSR1)
0x00_0284 (UCSR2)
7
R
W
Reset:
Note: The RCS and TCS reset values are set so the receiver and transmiter use the prescaled internal bus
clock as their clock source.
Field
7–4
Receiver clock select. Selects the clock source for the receiver.
RCS
1101 Prescaled internal bus clock (f
1110 DTINn divided by 16
1111 DTINn
3–0
Transmitter clock select. Selects the clock source for the transmitter.
TCS
1101 Prescaled internal bus clock (f
1110 DTINn divided by 16
1111 DTINn
24.3.5
UART Command Registers (UCRn)
The UCRs, shown in
Figure
conflict can be specified in a single write to a UCRn. For example,
cannot be specified in one command.
TRANSMITTER
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
Table 24-5. USRn Field Descriptions (continued)
6
5
RCS
See Note
Figure 24-6. UART Clock Select Registers (UCSRn)
Table 24-6. UCSRn Field Descriptions
)
sys
)
sys
24-7, supply commands to the UART. Only multiple commands that do not
Description
Section 24.4.1, "Transmitter/Receiver
4
3
Description
RESET TRANSMITTER
UART Modules
Access: User write-only
2
1
TCS
See Note
and
ENABLE
0
24-9
Advertisement
Chapters
Table of Contents
