Sdram Chip Select Configuration Registers - Freescale Semiconductor MCF5329 Reference Manual

SDRAM Controller (SDRAMC)
Field
31–28 Burst read to read/precharge delay. Limiting case is read to read.
BRD2RP SDR: BRD2RP = BurstLength + 1
DDR: BRD2RP = BurstLength/2 + 1
27–24 Burst write to read/write/precharge delay. Limiting case is write to precharge.
BWT2RWP SDR: BWT2RWP = BurstLength + t
DDR: BWT2RWP = BurstLength/2 + t
23–20 Burst read to write delay.
BRD2W SDR: BRD2W = CL + BurstLength
DDR: BRD2W = CL + BurstLength/2 - 1
19–16 Burst length.
BL BL = BurstLength - 1
Note: Burst length depends on port sizeIf 32-bit bus (SDCR[MEM_PS] = 0), burst length is 4. Write BL = 3.. If
16-bit bus (SDCR[MEM_PS] = 1), burst length is 8. Write BL = 7.
15–0 Reserved, must be cleared.
18.4.5 SDRAM Chip Select Configuration Registers (SDCSn)
These registers define base address and space size of each chip select.
Because the SDRAM module is one of the slaves connected to the crossbar
switch, it is only accessible within a certain memory range. The only
applicable address ranges for which the chip-selects can be active are
0x4000_0000 – 0x7FFF_FFFF. Be sure to set the SDCSn registers
appropriately.
The user should not probe memory on a DDR chip select to determine if
memory is connected. If a read is attempted from a DDR SDRAM chip
select when there is no memory to respond with the appropriate DQS pulses,
the bus cycle hangs. Because no high level bus monitor exists on the device,
a reset is the only way to exit the error condition.
Address: 0xFC0B_8110 (SDCS0)
0xFC0B_8114 (SDCS1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-9. SRAM Chip Select Configuration Register (SDCSn)
18-20
Table 18-10. SDCFG2 Field Descriptions
- 2
WR
WR
+ t
HZ
NOTE
NOTE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CSBA
MCF5329 Reference Manual, Rev 3
Description
8
Access: User read/write
7 6 5 4 3 2 1 0
CSSZ
Freescale Semiconductor