Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1726

Architectural Concepts
mapped to addresses 0x5000_0000 to 0x5FFF_FFFF). The Internal Address Translation Unit (iATU) enables the
mapping of these 256 MB to anywhere in the PCIe memory space.
Table 29-8: ADSP-SC58x System Component Memory Address Map
ADSP-SC58x System Component Memory
Address Map
Memory Sub-division
PCIe Data 256MB
SCB Slave Port Features
• Address bus width is 32-bit
• Data bus width is 32-bit
• Only incremental bursts are supported
• Maximum allowable burst length is 16 Beats
• Graceful flush and reset when link is down
• No exclusive access support
• No write interleaving with reads
• No write interleaving with writes of different AWIDs
• Outbound write burst with zero or partial (but contiguous) write strobes set is only supported for the first and
last beats of a burst.
• All accesses are memory accesses (always posted)
• Write responses are generated by the PCIe core after the write request and are received
• PCIe Advanced Error Reporting (AER) is not supported. AER is only supported with respect to the native
PCIe core. Errors detected by the bridge are not reported as part of AER.
• Read requests above the 256 Bytes limit are not supported
29–22
ARM View
All Accesses
Byte
Group range --> 0000_0000-
FFFF_FFFF
5000_0000 5007_FFFF
5008_0000 5017_FFFF
5018_0000 57FF_FFFF
5800_0000 5FFF_FFFF
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
System View
All Accesses Data Accesses
Byte Byte
2000_0000- 2000_0000-
FFFF_FFFF FFF_FFFF
5000_0000 5007_FFFF
5008_0000 5017_FFFF
5018_0000 57FF_FFFF
5800_0000 5FFF_FFFF
SHARC View
Code Execution
NW VISA
100_0000- 80_0000-
1FFF_FFFF FF_FFFF
5000_0000 5007_FFFF
5008_0000 5017_FFFF
5018_0000 57FF_FFFF
5800_0000 5FFF_FFFF
Non-VISA
40_0000-
7F_FFFF
200_0000
202_0000
206_0000
N/A