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Texas Instruments TAS5805M Manual

Texas Instruments TAS5805M Manual

23-w, inductor-less, digital input, stereo, closed-loop class-d audio amplifier with enhanced processing and low idle power dissipation

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TAS5805M 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio
Amplifier with Enhanced Processing and Low Idle Power Dissipation
1 Features
Supports Multiple Output Configurations
1
– 2 × 23 W in 2.0 Mode (8-Ω, 21 V, THD+N=1%)
– 45 W in Mono Mode (4-Ω, 21 V, THD+N=1%)
Excellent Audio Performance
– THD+N ≤ 0.03% at 1 W, 1 kHz, PVDD = 12 V
– SNR ≥ 107 dB (A-weighted), Noise Level < 40
µV
RMS
Low Quiescent Current with Hybrid Modulation
– 16.5 mA at PVDD = 13.5 V , 22 µH + 0.68 µF
Filter
Flexible Power Supply Configurations
– PVDD: 4.5 V to 26.4 V
– DVDD and I/O: 1.8 V or 3.3 V
Flexible Audio I/O
2
– I
S, LJ, RJ, TDM, 3-Wire Digital Audio
Interface (No MCLK Required)
– Supports 32, 44.1, 48, 88.2, 96 kHz Sample
Rates
– SDOUT for Audio Monitoring, Sub-Channel or
Echo Cancellation
Enhanced Audio Processing
– Multi-Band Advanced DRC and AGL
– 2×15 BQs, Thermal Foldback, DC Blocking
– Input Mixer, Output Crossbar, Level Meter
– 5 BQs + 1 Band DRC +THD Manager for the
Subwoofer Channel
Integrated Self-Protection
– Adjacent Pin to Pin Short Without Device
Damage
– Over-Current Error (OCE)
– Over-Temperature Warning (OTW)
– Over-Temperature Error (OTE)
– Under/Over-Voltage Lock-out (UVLO/OVLO)
Easy System Integration
2
– I
C Software Control
– Reduced Solution Size
– Fewer Passives Required Compared to
Open-Loop Devices
– Inductor-less Operation (Ferrite Bead) for
most cases where PVDD ≤ 14V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Order
Product
Technical
Folder
Now
Documents
Support &
Tools &
Community
Software
SLASEH5A – MAY 2018 – REVISED JULY 2018
2 Applications
LCD TV, OLED TV
Wireless Speaker, Smart Speaker with Voice
Assistant
Soundbar, Wired Speaker , Bookshelf Stereo
System
Desktop PC, Notebook PC
AV Receiver, Smart Home and IoT Appliance
3 Description
The TAS5805M is a high-efficiency, stereo, closed-
loop Class-D amplifier offering a cost effective digital-
input solution with low power dissipation and sound
enrichment. The device's integrated audio processor
and 96 kHz architecture supports advanced audio
process flow, including SRC, 15 BQs per channel,
volume control, audio mixing, 3-band 4th order DRC,
full-band AGL, THD managing and level meter.
Featuring TI's proprietary Hybrid Modulation scheme,
the TAS5805M consumes very-low quiescent current
(<16.5 mA at 13.5V PVDD), extending battery life in
portable audio applications. With advanced EMI
suppression technology, designers can leverage
inexpensive ferrite bead filters to reduced board
space and system cost.
Device Information
PART NUMBER
PACKAGE
TAS5805M
TSSOP (28) PWP
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
Speaker
L Channel
DVDD
System
Processor
TAS5805M
(1)
BODY SIZE (NOM)
9.7 mm × 4.4 mm
Speaker
R Channel
Digital
Audio
Source
Copyright © 2018, Texas Instruments Incorporated

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Summary of Contents for Texas Instruments TAS5805M

  • Page 1 Community Folder Software Documents TAS5805M SLASEH5A – MAY 2018 – REVISED JULY 2018 TAS5805M 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio Amplifier with Enhanced Processing and Low Idle Power Dissipation 1 Features 2 Applications • Supports Multiple Output Configurations •...
  • Page 2 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2018) to Revision A Page • Released as Production Data..............................Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 3 (1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 4 Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side BST_B+ gate drive for OUT_B+ OUT_B+ Positive pin for differential speaker amplifier output B+ PowerPAD™ Connect to the system Ground Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 5 °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bot) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 6 Amplifier gain error Gain = 29.5 Vp/FS V(SPK_AMP) Switching frequency of the SPK_AMP speaker amplifier Drain-to-source on resistance of the individual output FET + Metallization mΩ DS(on) MOSFETs Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 7 Ω, f = 1kHz, THD+N = 1%, BD Mode = 18 V, SPK_GAIN = 22.1 Vp/FS, R PVDD Ω, f = 1kHz, THD+N = 10%, BD Mode Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 8 A-Weighted, referenced to 1% THD+N output level, PVDD=24V Injected Noise = 1 KHz, 1 V = 19 V, input Power supply rejection ratio audio signal = digital zero Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 9 Rise time of SDA signal 20 + 0.1C SDA-R Fall time of SDA signal 20 + 0.1C SDA-F Setup time for STOP condition P-SU Pulse width of spike suppressed Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 10 10uH+0.68uF = 768 kHz 1SPW Modulation Load = 6Ω = 768 kHz 1SPW Modulation Load = 6Ω Figure 5. THD+N vs Frequency-BTL Figure 6. THD+N vs Frequency-BTL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 11 1SPW Modulation Load = 4Ω = 768 kHz 1SPW Modulation Load = 6Ω Figure 11. Output Power vs Supply Voltage-BTL Figure 12. Output Power vs Supply Voltage-BTL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 12 = 768 kHz 1SPW Modulation Load = 6Ω = 768 kHz 1SPW Modulation Load = 6Ω Figure 17. THD+N vs Output Power-BTL Figure 18. THD+N vs Output Power-BTL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 13 PVDD = 18V 10uH+0.68uF Pout=1W = 768 kHz 1SPW Modulation Load = 6Ω = 768 kHz 1SPW Modulation Load = 6Ω Figure 23. Crosstalk Figure 24. Crosstalk Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 14 = 768 kHz 1SPW Modulation Load = 4Ω = 768 kHz 1SPW Modulation Load = 6Ω Figure 29. Efficiency vs Output Power-BTL Figure 30. Efficiency vs Output Power-BTL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 15 = 384 kHz BD Modulation Load = 8Ω = 384 kHz BD Modulation Load = 4Ω Figure 34. Output Power vs Supply Voltage-BTL Figure 35. THD+N vs Output Power-BTL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 16 1 kHz and device PWM frequency set to 576 kHz, the LC filter used was 4.7 μH / 0.68 μF, unless otherwise noted. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 17 = 576 kHz 1SPW Modulation Load = 4Ω = 576 kHz 1SPW Modulation Load = 4Ω Figure 46. THD+N vs Output Power-PBTL Figure 47. THD+N vs Output Power-PBTL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 18 = 24 V Output Power (W) D043 D156 PVDD = 5V/7.4V/12V/18V/24V 4.7uH + 0.68uF = 576 kHz 1SPW Modulation Load = 4Ω Figure 52. Efficiency vs Output Power Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 19 Figure 53. Serial Audio Port Timing in Slave Mode Repeated START STOP START D-SU D-HD SDA-F P-SU SDA-R BUF. SCL-R. RS-HD LOW. RS-SU S-HD. SCL-F. Figure 54. I C Communication Port Timing Diagram Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 20 9 Detailed Description 9.1 Overview The TAS5805M device integrates 4 main building blocks together into a single cohesive device that maximizes sound quality, flexibility, and ease of use. The 4 main building blocks are listed as follows: • A stereo audio DAC.
  • Page 21 9.3 Feature Description 9.3.1 Power Supplies To facilitate system design, TAS5805M needs only a 3.3-V or 1.8-V supply in addition to the (typical) 12-V or 24- V power-stage supply. Two internal voltage regulators provide suitable voltage levels for the gate drive circuitry and internal circuitry.
  • Page 22 Audio data word = 24-bit, SCLK = 64f DATA 23 24 23 24 Audio data word = 32-bit, SCLK = 64f DATA 31 32 31 32 Figure 56. Left-Justified Audio Data Format Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 23 31 32 31 32 Right-Justified Data Format; L-channel = HIGH, R-channel = LOW Right-Justified Data Format; L-channel = HIGH, R-channel = LOW Figure 58. Right-Justified Audio Data Format Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 24 TDM Data Format with OFFSET = 1 In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start. Figure 60. TDM 2 Audio Data Format Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 25 Figure 61, the audio path of the TAS5805M consists of a digital audio input port, a digital audio path, a digital to PWM converter (DPC), a gate driver stage, a Class-D power stage, and a feedback loop which feeds the output information back into the DPC block to correct for distortion sensed on the output pins.
  • Page 26 The process is called Post-Filter PBTL. On the input side of the TAS5805M device, the input signal to the PBTL amplifier is left frame of I2S or TDM data.
  • Page 27 This mode can be used to extend the battery life in some portable speaker applications. If the host processor stops playing audio for a long time, TAS5805M can be set to Deep Sleep Mode to minimize power dissipation until host processor starts playing audio again. Device returns back to Play Mode by setting Register 0x03h -D[1:0] to 11.
  • Page 28 The result is that only one output is switching during a majority of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 29 Hybrid Modulation is designed for minimized power loss without compromising the THD+N performance, and is optimized for battery-powered applications. With Hybrid modulation, TAS5805M will detect the input signal level and adjust PWM duty cycle dynamically based on PVDD. Hybrid modulation achieves ultra low idle current and maintains the same audio performance level as the Hybrid Modulation.
  • Page 30 9.5.2 Slave Address The TAS5805M device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are factory preset to 01011(0x5x). The next two bits of address byte are the device select bits which can be user-...
  • Page 31 Acknowledge Condition Acknowledge A1 A0 C Device Address C Device Address Stop Subaddress Data Byte and R/W Bit and R/W Bit Condition Figure 66. Random Read Transfer Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 32 The address of all Biquad Filters can be found in Register Maps All DSP/Audio Process Flow Related Register are listed in Application Note, TAS5805M Process Flows 9.5.2.6 Checksum This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum and an Exclusive (XOR) checksum.
  • Page 33 FETs, and operation returns to normal after the short is removed. 9.5.3.3.2 DC Detect If the TAS5805M device measures a DC offset in the output voltage, the FAULTZ line is pulled low and the OUTxx outputs transition to high impedance, signifying a fault.
  • Page 34 Register 110 SS_CTRL4 Register 111 CHAN_FAULT Register 112 GLOBAL_FAULT1 Register 113 GLOBAL_FAULT2 Register 114 OT WARNING Register 115 PIN_CONTROL1 Register 116 PIN_CONTROL2 Register 117 MISC_CONTROL Register 118 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 35 Table 6. CONTROL PORT Access Type Codes Access Type Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 36 Reset Registers This bit resets the control port registers back to their initial values. The RAM content is not cleared. 0: Normal 1: Reset control port registers Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 37 101:Reserved 110:Reserved 111:Reserved RESERVED This bit is reserved DAMP_PBTL 0: SET DAMP TO BTL MODE 1:SET DAMP TO PBTL MODE DAMP_MOD 00:BD MODE 01:1SPW MODE 10:HYBRID MODE Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 38 0: Normal volume 1: Mute RESERVED This bit is reserved CTRL_STATE device state control register 00: Deep Sleep 01: Sleep 10: Hiz, 11: PLAY Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 39 4 'b0000 Auto detection 4 'b0010 8KHz 4 'b0100 16KHz 4 'b0110 32KHz 4 'b1000 44.1KHz 4'b1001 48KHz 4 'b1010 88.2KHz 4 'b1011 96KHz Others Reserved Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 40 9.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h] SDOUT_SEL is shown in Figure 74 and described in Table Return to Summary Table. Figure 74. SDOUT_SEL Register RESERVED SDOUT_SEL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 41 SDOUT_SEL SDOUT Select. This bit selects what is being output as SDOUT pin. 0: SDOUT is the DSP output (post-processing) 1: SDOUT is the DSP input (pre-processing) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 42 BCK. Normally they are assumed to be aligned to the falling edge of the BCK. 0: Normal BCK mode 1: Inverted BCK mode RESERVED 00000 This bit is reserved Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 43 (MSB) of audio frame to the starting of the desired audio sample. 000000000: offset = 0 BCK (no offset) 000000001: ofsset = 1 BCK 000000010: offset = 2 BCKs 111111111: offset = 512 BCKs Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 44 Right DAC Data Path. These bits control the right channel audio data path connection. 00: Zero data (mute) 01: Right channel data 10: Left channel data 11: Reserved (do not set) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 45 Type Reset Description BCLK_RATIO_LOW 00000000 These bits indicate the currently detected BCK ratio, the number of BCK clocks in one audio frame. BCK = 32 FS~512 FS Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 46 24 dB to -103 dB in -0.5 dB step. 00000000: +24.0 dB 00000001: +23.5 dB ..and 00101111: +0.5 dB 00110000: 0.0 dB 00110001: -0.5 dB ..11111110: -103 dB 11111111: Mute Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 47 00: Increment by 4 dB for each updat e 01: Increment by 2 dB for each update 10: Increment by 1 dB for each update 11: Increment by 0.5 dB for each update Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 48 0: Auto mute left channel and right channel independently. 1: Auto mute left and right channels only when both channels are about to be auto muted. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 49 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 50 "00": 80kHz; "01": 100kHz; "10": 120kHz; "11": 175kHz. With Fsw=768kHz, 175kHz bandwidth should be selected for high audio performance. bit4: Reserved bit3: Reserved bit2~1: Reserved bit0: Reserved Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 51 Table 28. BQ_WR_CTRL1 Register Field Descriptions Field Type Reset Description RESERVED 0000000 This bit is reserved BQ_WR_FIRST_COEF Indicate the first coefficient of a BQ is starting to write. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 52 RESERVED 0000000 This bit is reserved ADR_OE ADR Output Enable This bit sets the direction of the ADR pin 0: ADR is input 1: ADR is output Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 53 9.6.1.27 DIE_ID Register (Offset = 67h) [reset = 0h] DIE_ID is shown in Figure 94 and described in Table Return to Summary Table. Figure 94. DIE_ID Register DIE_ID R-0h Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 54 TAS5805M SLASEH5A – MAY 2018 – REVISED JULY 2018 www.ti.com Table 33. DIE_ID Register Field Descriptions Field Type Reset Description DIE_ID DIE ID Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 55 Figure 95. POWER_STATE Register STATE_RPT Table 34. POWER_STATE Register Field Descriptions Field Type Reset Description STATE_RPT 00000000 0: Deep sleep 1: Seep 2: HIZ 3: Play Others: reserved Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 56 This bit indicates the auto mute status for right channel. 0: Not auto muted 1: Auto muted ZERO_LEFT_MON This bit indicates the auto mute status for left channel. 0: Not auto muted 1: Auto muted Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 57 10: phase2 11: phase3 I2S_SYNC_EN Use I2S to synchronize output PWM phase 0: Disable 1: Enable PHASE_SYNC_EN 0: RAMP phase sync disable 1: RAMP phase sync enable Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 58 Table 38. SS_CTRL1 Register Field Descriptions Field Type Reset Description RESERVED This bit is reserved SS_RDM_CTRL random SS range control SS_TRI_CTRL 0000 triangle SS frequency and range control Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 59 This bit is reserved TM_AMP_CTRL control ramp amp ctrl in ramp ss manual model SS_TM_PERIOD_BOUN 00100 control triangle mode spread spectrum boundary in ramp ss manual mode Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 60 Indicate OTP CRC check error. BQ_WR_ERROR the recent BQ is written failed RESERVED This bit is reserved CLK_FAULT_I clock fault PVDD_OV_I PVDD OV fault PVDD_UV_I PVDD UV fault Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 61 Table 45. OT_WARNING Register Field Descriptions Field Type Reset Description RESERVED This bit is reserved RESERVED This bit is reserved over temperature warning ,130C RESERVED This bit is reserved Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 62 This bit is reserved CLKFLT_LATCH_EN enable clock fault latch OTSD_LATCH_EN enable OTSD fault latch OTW_LATCH_EN enable OT warning latch MASK_OTW mask OT warning report RESERVED This bit is reserved Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 63 Description DET_STATUS_LATCH 1:latch clock detection status 0:don't latch clock detection status RESERVED This bit is reserved OTSD_AUTO_REC_EN OTSD auto recovery enable RESERVED 0000 This bit is reserved Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 64 Table 49. FAULT_CLEAR Register Field Descriptions Field Type Reset Description ANALOG_FAULT_CLEAR W WRITE CLEAR BIT. Once write this bit to 1, device will clear analog fault RESERVED 0000000 This bit is reserved Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 65 10.1.3 Output EMI Filtering The TAS5805M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive element L and a capacitive element C to make up the 2-pole filter.
  • Page 66 SLASEH5A – MAY 2018 – REVISED JULY 2018 www.ti.com Typical Applications (continued) Figure 111. 2.0 (Stereo BTL) System Application Schematic with Ferrite Bead as the output filter Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 67 Communication: host processor serving as I C compliant master • External memory (Such as EEPROM and FLASH) used for coefficients The requirement for the supporting components for the TAS5805M device in a Stereo 2.0 (BTL) system is provide in Table 50 Table 51 Table 50.
  • Page 68 Ferrite Bead, 100 ohm @ 100 MHz, 4 A, 0806 With Low EMI technology, TAS5805M keeps enough EMI margin for most of application cases where PVDD < 14V with ferrite bead (Low BOM cost). With Ferrite Bead and capacitor as the output filter,...
  • Page 69 With Inductor as the output filter, designers can achieve ultra low idle current (with Hybrid Modulation or 1SPW Modulation) and keep large EMI margin. As the switching frequency of TAS5805M can be adjustable from 384kHz to 768kHz. Higher switching frequency means smaller Inductor value needed.
  • Page 70 Radiated Emission. More data are included in the application note -TAS5805M Design Considerations for EMC. 10.2.2 MONO (PBTL) Systems In MONO mode, TAS5805M can be used as PBTL mode to drive sub-woofer with more output power. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 71 • External memory (Such as EEPROM and FLASH) used for coefficients The requirement for the supporting components for the TAS5805M device in a MONO (PBTL) system is provide Table 52 Table 52. Supporting Component Requirements for MONO (PBTL) system (With Inductor as output...
  • Page 72 In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was done in the high-frequency channels. To accomplish this, two TAS5805M devices are used - one for the high frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can be sent from the TAS5805M device through the SDOUT pin.
  • Page 73 TAS5805M www.ti.com SLASEH5A – MAY 2018 – REVISED JULY 2018 Figure 122. 2.1 (2.1 CH with Two TAS5805M Devices) Application Schematic Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 74 11 Power Supply Recommendations The TAS5805M device requires two power supplies for proper operation. A high-voltage supply calls PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low- voltage power supply which is calls DVDD is required to power the various low-power portions of the device. The allowable voltage range for both PVDD and DVDD supply are listed in the Recommended Operating Conditions table.
  • Page 75 Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD. AVDD pin is provided for the attachment of decoupling capacitor for the TAS5805M internal circuitry. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry.
  • Page 76 Placement of these components too far from the TAS5805M device can cause ringing on the output pins that can cause the voltage on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the deice .
  • Page 77 The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the shape and position of the copper patterns to which the TAS5805M device will be soldered. This footprint can be followed directly from the guidance in the package addendum at the end of this data sheet. It is important to make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™...
  • Page 78 Figure 124. 2.0 (Stereo BTL with Ferrite Bead as Output Filter) Layout View Top Layer 3D view Top Layer Layout Bot Layer 3D view Bot Layer Layout Figure 125. 2.0 (Stereo BTL with Inductor as Output Filter) Layout View Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 79 Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: TAS5805M...
  • Page 80 TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.4 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. 13.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
  • Page 81 PACKAGE OPTION ADDENDUM www.ti.com 19-Sep-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) TAS5805MPWP ACTIVE HTSSOP Green (RoHS CU NIPDAU Level-3-260C-168 HR -25 to 85 TAS5805MA1 &...
  • Page 82 PACKAGE OPTION ADDENDUM www.ti.com 19-Sep-2018 Addendum-Page 2...
  • Page 83 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) TAS5805MPWPR HTSSOP 2000 330.0 16.4 10.2 12.0 16.0 Pack Materials-Page 1...
  • Page 84 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2018 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) TAS5805MPWPR HTSSOP 2000 367.0 367.0 38.0 Pack Materials-Page 2...
  • Page 86 TYPICAL 3.10 2.58 4224480/A 08/2018 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice.
  • Page 87 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
  • Page 88 EXAMPLE STENCIL DESIGN PWP0028M PowerPAD TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE (3.1) BASED ON 28X (1.5) 0.125 THICK METAL COVERED STENCIL BY SOLDER MASK 28X (0.45) (R0.05) TYP 26X (0.65) (4.05) SYMM BASED ON 0.125 THICK STENCIL SYMM SEE TABLE FOR DIFFERENT OPENINGS...
  • Page 89 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated...