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6. ROM
6.6.2
Software Protection
Software protection can be implemented by setting the SWE bit in flash memory control register 1
(FLMCR1), and the erase block register (EBR). With software protection, setting the P or E bit in
FLMCR1 does not cause a transition to program mode or erase mode. (See table 6.8.)
Table 6.8
Software Protection
Item
Description
•
SWE bit
Clearing the SWE bit to 0 in FLMCR1 sets
protection
the program/erase-protected state for all
blocks. (Execute in on-chip RAM.)
•
Block
Individual blocks can be protected from
protection
erasing and programming by settings in the
erase block register (EBR)*
•
If H'00 is set in EBR, all blocks are protected
from erasing and programming.
Notes: 1. Two modes: program-verify and erase-verify.
2. When not erasing, clear all EBR bits to 0.
6.6.3
Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing*
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. FLMCR1, FLMCR2, and EBR settings*
retained, but program mode or erase mode is aborted at the point at which the error occurred.
Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and
EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
1. When flash memory is read*
instruction fetch)
2. Immediately after the start of exception handling (excluding a reset) during
programming/erasing*
Rev.3.00 Jul. 19, 2007 page 146 of 532
REJ09B0397-0300
1
, or operation is not performed in accordance with the program/erase
3
during programming/erasing (including a vector read or
4
Program Erase
Not
possible
⎯
2
.
Functions
1
Verify*
Not
Not
possible
possible
Not
Possible
possible
2
are
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