Slave Address Transmission - Freescale Semiconductor MCF52277 Reference Manual

2
I C Interface
msb
I2C_SCL
1
I2C_SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
A
START
Signal
31.3.2

Slave Address Transmission

The master sends the slave address in the first byte after the START signal (B). After the seven-bit calling
address, it sends the R/W bit (C), which tells the slave data transfer direction (0 equals write transfer, 1
equals read transfer).
Each slave must have a unique address. An I
be master and slave at the same time.
The slave whose address matches that sent by the master pulls I2C_SDA low at the ninth serial clock (D)
to return an acknowledge bit.
31.3.3 Data Transfer
When successful slave addressing is achieved, data transfer can proceed (see E in
byte-by-byte basis in the direction specified by the R/W bit sent by the calling master.
Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high, as
Figure 31-7 shows. I2C_SCL is pulsed once for each data bit, with the msb being sent first. The receiving
device must acknowledge each byte by pulling I2C_SDA low at the ninth clock; therefore, a data byte
transfer takes nine clock pulses. See
I2C_SCL
1 2
I2C_SDA
Bit7 Bit6
START
Signal
31-8
(Byte complete)
2 3 4 5 6 7
Calling Address
B
2
Figure 31-7. I C Standard Communication Protocol
2
Figure 31-8.
3 4 5 6 7
Bit5 Bit4 Bit3 Bit2 Bit1
Slave Address
Figure 31-8. Data Transfer
MCF52277 Reference Manual, Rev. 1
I2C_SCL held low while
Interrupt bit set
Interrupt is serviced
lsb msb
8 9 1 2
XXX D7 D6
ACK
R/W
E
Bit
C D
C master must not transmit its own slave address; it cannot
I2C_SCL held low while
Interrupt is serviced
8 9 1 2
Interrupt Bit Set
(Byte Complete)
Bit0
Bit7 Bit6 Bit5
R/W
ACK from
Receiver
lsb
3 4 5 6 7 8
D5 D4 D3 D2 D1 D0
Data Byte
Figure 31-7) on a
3 4 5 6 7 8
Bit4 Bit3 Bit2 Bit1 Bit0
Data Byte
Freescale Semiconductor
9
No
STOP
ACK Signal
Bit
F
9
No
STOP
ACK Bit
Signal