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Interrupt Controller Module
14.3.1
Interrupt Pending Registers (IPRHn, IPRLn)
The IPRHn and IPRLn registers,
interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given
source. The state of the interrupt mask register does not affect the IPRn. The IPRn is cleared by reset. The
IPRn is a read-only register, so any attempted write to this register is ignored. Bit 0 is not implemented and
reads as a zero.
IPSBAR
Offset: 0x0C00 (IPRHn)
31
30
29
R
W
Reset
0
0
15
14
13
R
W
Reset
0
0
Field
31–0
Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an
INT
interrupt condition can generate an interrupt. At every system clock, the IPRHn samples the signal generated by the
interrupting source. The corresponding IPRHn bit reflects the state of the interrupt signal even if the corresponding
IMRHn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
IPSBAR
Offset: 0x0C04 (IPRLn)
31
30
29
R
W
Reset
0
0
15
14
13
R
W
Reset
0
0
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
14-6
Figure 14-1
28
27
26
0
0
0
0
12
11
10
0
0
0
0
Figure 14-1. Interrupt Pending Register High (IPRHn)
Table 14-3. IPRHn Field Descriptions
28
27
26
0
0
0
0
12
11
10
0
0
0
0
Figure 14-2. Interrupt Pending Register Low (IPRLn)
and
Figure
14-2, each 32 bits, provide a bit map for each
25
24
23
22
INT[63:48]
0
0
0
0
9
8
7
6
INT[47:32]
0
0
0
0
Description
25
24
23
22
INT[31:16]
0
0
0
0
9
8
7
6
INT[15:1]
0
0
0
0
Access: Read-only
21
20
19
18
0
0
0
0
5
4
3
2
0
0
0
0
Access: Read-only
21
20
19
18
0
0
0
0
5
4
3
2
0
0
0
0
Freescale Semiconductor
17
16
0
0
1
0
0
0
17
16
0
0
1
0
0
0
0
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