Siu Interrupt Mask Register (Simask) - Freescale Semiconductor MPC850 User Manual

10.5.4.2 SIU Interrupt Mask Register (SIMASK)

Bits in SIMASK correspond to the interrupt request bits in SIPEND. Setting SIMASK bits
enable the generation of interrupt requests to the core. SIMASK is updated by the software,
which must determine which interrupt sources are enabled at a given time.
Bit 0 1 2
Field IRM0 LVM0 IRM1 LVM
Reset
R/W
Addr
Bit 16 17 18
Field
Reset
R/W
Addr
Figure 10-11. SIU Interrupt Mask Register (SIMASK)
Table 10-10 describes SIMASK fields.
Bits Name
0 IRM0 Interrupt request mask 0. Enables/disables updating SIVEC[INTC]. IRQ0 generates an NMI
regardless of this bit.
1, 3, 5, LVMn Level mask 0–7. When set, these bits enable an internal interrupt request to be generated.
7, 9, 11, 0 Disable generation of an interrupt request bit in SIPEND.
1 Enable generation of an interrupt request bit in SIPEND.
13, 15
2, 4, 6, IRMn Interrupt request mask 1–7. When set, these bits enable an IRQ interrupt request to be generated.
8, 10, 0 Disable generation of an interrupt request bit in SIPEND.
1 Enable generation of an interrupt request bit in SIPEND.
12, 14
16–31 — Reserved, should be cleared.
The following procedure prevents possible interrupt errors when modifying mask registers,
such as SIMASK:
1. Clear MSR[EE]. (Disable external interrupts to the core.)
2. Modify the mask register.
3. Set MSR[EE]. (Enable external interrupts to the core.)
This mask modification procedure ensures that an already pending interrupt is not masked
before being serviced.
3 4 5 6
IRM2 LVM2 IRM3 LVM3 IRM4 LVM4 IRM5 LVM5 IRM6 LVM6 IRM7 LVM7
1
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x014
19 20 21 22
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x016
Table 10-10. SIMASK Field Descriptions
Chapter 10. System Interface Unit
7 8 9 10
R/W
23 24 25 26
—
R/W
Description
System Configuration
11 12 13 14
27 28 29 30
15
31